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研究生: 蔡輔桓
Tsai, Fu-Huan
論文名稱: 應用電荷汲引技術於先進金氧半電晶體高介電閘層之缺陷探測分析研究
Study of Profiling Traps in High-k Gate Dielectric for Advanced MOSFETs by Applying Charge Pumping Technique
指導教授: 張廖貴術
Chang-Liao, Kuei-Shu
口試委員: 楊文祿
趙天生
學位類別: 碩士
Master
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 93
中文關鍵詞: 電荷汲引技術可靠度電晶體高介電系數介電層溫度電應力
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  • 以高介電係數材料取代二氧化矽成為金氧半元件閘極介電層來改善元件微小化伴隨的漏電流問題,然而在材料替換的過程中,產生許多額外的問題。如電荷捕獲,臨界電壓飄移,載子遷移率下降等,因此應用在高介電係數閘極介電層電晶體上的界面陷阱及氧化層陷阱可靠度分析因應而生。
    論文首先介紹電荷汲引技術(charge pumping)的基本原理與量測方法,藉由載子的捕捉與複合得到之淨電流,稱為汲引電流(Icp)。將不同的汲引電流換算後可得到對應的界面陷阱密度與能量分佈狀況,以及得到邊緣陷阱密度與空間分佈的關係。
    其次說明,傳統電荷汲引方式中存在量測延遲上的問題,界面陷阱容易因為快速的回復行為而使量測到的結果產生誤差。遂利用不間斷的連續脈波同時施加應力與量測,達到不間斷量測的方式,成功觀察到界面缺陷的快速回復過程並藉以獲得較正確的界面缺陷密度。
    接著分析經過Fluorine電漿介面處理元件的BTI可靠度表現,使用氟電漿處理與700oC沉積後退火溫度者有最佳的可靠度表現。然後藉由電荷分離與電荷汲引技術,分離PBTI與NBTI後不同缺陷對臨界電壓飄移的貢獻,儘管在NBTI中有較大量的界面缺陷增生,卻只在PBTI中觀察到明顯的臨界電壓飄移,表示主要影響臨界電壓飄移的為氧化層缺陷的電荷捕捉而非界面缺陷密度。
    最後討論進行BTI可靠度量測時,所需注意的量測溫度選擇問題,當給定量的缺陷數目下,在不同量測溫度下量測會因臨界電壓的變動而造成高估或低估電應力結果。並且改變溫度亦會產生額外的溫度效應,造成臨界電壓回復現象。因此進行BTI的電應力實驗時,在量測溫度的選擇上,除了保持相同的起點與終點溫度。還必須在與應力溫度相同的溫度下進行,避免量測溫度效應。對擷取缺陷活化能與評估可靠度上有著不可或缺的影響。


    摘要 Ⅰ 致謝 Ⅲ 目錄 Ⅳ 圖表目錄 Ⅶ 第一章 序論 1 1.1 研究動機 1 1.2 高介電係數材料選擇 1 1.3電荷汲引量測技術 2 1.4論文大綱 3 第二章 應用電荷汲引量測技術分析High-κ介電層電晶體陷阱分佈 6 2.1研究動機 6 2.2 界面陷阱密度與能量分佈 (Energy Distribution of Interface Trap Density) 7 2.2.1 基本電荷汲引量測技術 7 2.2.2 陷阱捕捉截面(Capture Cross Section, σ)的計算 8 2.2.3 High-κ電晶體界面陷阱密度能量分佈 10 2.2.4量測結果與討論 11 2.3邊緣陷阱密度縱深分佈的量測 (Depth Profiles of Border Trap Density) 11 2.3.1 高介電係數電晶體的邊緣陷阱 11 2.3.2量測方法與量測裝置 11 2.3.3 縱深分布公式與計算 12 2.3.4量測結果與討論 13 2.4結論 14 第三章 應用快速電荷汲引方法分析MOS可靠度之研究 26 3.1 研究動機 27 3.2 實驗方法與設置 28 3.3 脈波電應力之頻率響應 28 3.4界面缺陷的快速回復現象 29 3.5 脈波頻率與正脈波持續時間對界面缺陷行為的影響 31 3.5.1脈波頻率與正脈波持續時間對缺陷密度的影響 31 3.5.2頻率與正脈波持續時間對缺陷回復的影響 33 3.6結論 34 第四章 氟電漿界面處理與沉積後退火溫度製程其元件可靠度與增生缺陷之關聯 48 4.1研究動機 49 4.2氟電漿界面處理與沉積後退火溫度對可靠度改善的影響 50 4.2.1製程參數與實驗設置 50 4.2.2 沉積後退火溫度對可靠度的影響 50 4.2.3氟電漿處理對可靠度的影響 51 4.2.4 沉積後退火溫度與氟電漿處理 51 4.2.5總結 52 4.3界面缺陷與臨界電壓飄移 53 4.3.1利用電荷汲引技術分析界面缺陷 53 4.3.2以電荷分離技術分析氧化層缺陷與界面缺陷 55 4.3.3總結 56 4.4結論 57 第五章 BTI量測溫度引致之臨界電壓飄移回復現象 74 5.1研究動機 75 5.2高溫可靠度量測 76 5.3量測溫度與臨界電壓回復現象 77 5.3.1量測溫度選擇 77 5.3.2量測溫度差異產生之臨界電壓飄移 77 5.4循環電應力與臨界電壓回復現象 79 5.5 結論 81 第六章 結論 90 參考文獻 91

    [1] Wenjuan Zhu, et al., " Mobility Measurement and Degradation Mechanisms of MOSFETs Made With Ultrathin High-k Dielectrics," EDL, vol. 51, no. 1, pp. 98-105, 2004
    [2] A. Kerber, et al., “Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics,” EDL, vol. 24, pp. 87-89, 2003
    [3] J. S. Bruglar and P. G. A. Jaspers, "Charge Pumping in MOS Devices," T-ED, Vol.16, p.297, 1969
    [4] J. P. Han, et al., "Energy Distribution of Interface Traps in High-K Gated MOSFETs," VLSI, pp. 161-162, 2003
    [5] Y. Maneglia and D. Bauza, "Extraction of slow trap concentration profiles in metal-oxide-semiconductor transistors using the charge pumping method," JAP, vol. 79, pp. 4187–4192, 1996
    [6] S. Jakschik, et al., "Influence of Al2O3 dielectrics on the trap-depth profiles in MOS devices investigated by the charge-pumping method," T-ED, vol. 51, pp.2252-2255, 2004
    [7] Mickael Denais et al., “Interface Trap Generation and Hole Trapping Under NBTI and PBTI in Advanced CMOS Technology With a 2-nm Gate Oxide,” T-DMR, Vol. 4, no. 4, 2004
    [8] M.-F. Li et al., “Understand NBTI Mechanism by Developing Novel Measurement Techniques,” T-DMR, vol. 8, no. 1, pp. 62–71, 2008
    [9] W.J. Liu et al., “On-The-Fly Interface Trap Measurement and its Impact on the Understanding of NBTI Mechanism for p-MOSFETs with SiON Gate Dielectric,” IEDM, 2007.
    [10] Z.Y. Liu et al., “Comprehensive Studies of BTI Degradation in SiON Gate Dielectric CMOS Transistors by New Measurement Techniques,” IRPS, pp. 733-734, 2008
    [11] Ph. Hehenberger et al., “Do NBTI-Induced Interface States Show Fast Recovery? A Study Using a Corrected On-The-Fly Charge-Pumping Measurement Technique” IRPS, pp.1033-1038, 2009
    [12] M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs,” IEDM, pp. 14.4.1 - 14.4.4, 2003
    [13] V. Huard and M. Denais, “Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors,” IRPS, pp. 40, 2004.
    [14] H. Reisinger et al., “Analysis of NBTI degradation- and recovery-behavior based on ultra fast VT-measurements,” IRPS, pp. 448, 2006.
    [15] R. Fernandez et al., “AC NBTI studied in the 1 Hz – 2 GHz range on dedicated on-chip CMOS circuits,” IEDM, pp. 1-4, 2006
    [16] H.-H. Tseng et al., "Defect Passivation with Fluorine in a TaxCy/High-K Gate Stack for Enhanced Device Threshold Voltage Stability and Performance", IEDM, pp. 696-699, 2005
    [17] Woei-Cherng Wu et al., "Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation", IEDM, pp. 1-4, 2008
    [18] E.Y. Wu, et al, "Experimental evidence of tBD power-law for voltage dependence of oxide breakdown in ultrathin gate oxides", EDL, vol.49, no.12, pp. 2244-2253, 2002
    [19] R. Degraeve et al., "Degradation and breakdown of 0.9nm EOT SiO2/ ALD HfO2/metal gate stacks under positive Constant Voltage Stress", IEDM, pp. 408-411, 2005
    [20] M. Walters et al., "The distribution of radiation-induced charged defects and neutral electron traps in SiO2 and the threshold voltage shift dependence on oxide thickness", JAP, vol.45, pp. 2992-3002, 1990
    [21] D. Heh et al., "Experimental evidence of the fast and slow charge trapping/detrapping processes in high-k dielectrics subjected to PBTI stress", EDL, vol. 29, pp. 180-182, 2008
    [22] Gennadi Bersuker et al., "Mechanism of Electron Trapping and Characteristics of Traps in HfO2 Gate Stacks", T-DMR, vol. 7, no. 1, pp. 138-145, 2007
    [23] Daniele Ielmini, and Francesco Gattel, “Delay Correction for Accurate Extraction of Time Exponent and Activation Energy of NBTI,” EDL, vol. 30, no. 6, 2009
    [24] K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” JAP, vol. 48, no. 5, pp. 2004–2014, 1977
    [25] C. E. Blat, E. H. Nicollian, and E. H. Poindexter, “Mechanism of negative-bias-temperature instability,” JAP, vol. 69, no. 3, pp. 1712–1720, 1991
    [26] D.P. Ioannou et al., “PBTI response to Interfacial Layer Thickness variation in Hf-based HKMG nFETs,” IRPS, pp. 1044-1048, 2010
    [27] Hyung-Suk Jung et al., “The Bias Temperature Instability Characteristics of In Situ Nitrogen Incorporated ZrOxNy Gate Dielectrics,” ECS, vol. 13, no. 9, pp. G71-G74, 2010
    [28] J. F. Zhang, M. H. Chang, and G. Groeseneken, “Effects of Measurement Temperature on NBTI,” EDL, vol. 28, no. 4, 2007
    [29] Aravind Appaswamy et al., “Influence of Interface Traps on the Temperature Sensitivity of MOSFET Drain-Current Variations,” EDL, vol. 31, no. 5, 2010
    [30] G. Ribes et al., “Review on High-k Dielectrics Reliability Issues,” T-DMR, vol. 5, no. 1, pp. 5-19, 2005
    [31] Sriram Kalpat et al., “BTI Characteristics and Mechanisms of Metal Gated HfO2 Films With Enhanced Interface/Bulk Process Treatments,” T-DMR, vol. 5, no. 1, pp. 26-35, 2005

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