當傳統六個電晶體的靜態隨機處理記憶體的操作電壓低於電晶體的次臨界電壓時，位元線和記憶單元之間的分壓效應會在記憶單元內造成讀取時的干擾突波以及寫入時的半選擇干擾，進而影響電路穩定度，使得記憶單元易受雜訊干擾而損失資料。因此本篇論文提出九個電晶體架構之記憶單元，此單元無讀取和寫入時的分壓干擾，同時亦具有交叉位元的結構和雙端埠口操作的特色。
為了消除分壓效應所造成的干擾突波，一個額外的讀取路徑被設計用來隔絕記憶單元與位元線，可有效改善讀取時的靜態雜訊邊際。而此單元的交叉位元結構，改善寫入時所造成的半選擇干擾。除此之外，在運作的情形下亦支援雙端埠口的操作，具有同時寫入或讀寫的特色，可有效提升系統的操作速度避免冗餘時間的消耗。
同樣為了避免冗餘時間的消耗，在此目的下為了有效控制字組線，使字組線的脈波寬度能夠隨著不同的製程、電壓和溫度而做自適性的改變，我們亦設計複製單元去偵測操作完成的時間，在此架構下，非同步系統的操作較容易實現。
本篇論文使用台積電六五奈米低功率製程，在此製程下與相關研究比較，結果顯示出此篇論文提出的記憶單元具有較強健的穩定度、較小的操作時間以及較小的靜態功率，符合低電壓低功率的操作需求。

Static Random Access Memory (SRAM) cell stability is a key challenge in sub-threshold SRAM design, in which read disturb and half-select disturb have been major issues. In this thesis, we propose a 9T cell with 3key features, Static Noise Margin (SNM) free, dual-port access and bit-interleaving structure to eliminate half-select disturb.
With additional read port, it can isolate the storage node from bit-line during read access, thereby improving the SNM. The proposed cell also provides efficient bit-interleaving structure to avoid half-select disturb issue. In addition, the 9T SRAM cell can perform read and write operations simultaneously, hence dual-port SRAM function can be implemented with better efficiency. To be able to control the word-line efficiently, where the word-line pulse width varies at different process, voltage and temperature (PVT) conditions, we developed a dummy cell to detect the access completion both in read and write modes. Thus, the asynchronous operations can be achieved easily.
Using TSMC 65nm low-power spice models, the purposed cell is shown to reduce the access delay and achieve much smaller static power as compared to other approaches.

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