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研究生: 林庭寬
Lin, Ting-Kuan
論文名稱: 電阻式記憶體式脈衝神經網路的非線性校準
Calibration for Non-linearity of ReRAM-based SNN Operation
指導教授: 劉靖家
Liou, Jing-Jia
口試委員: 黃稚存
Huang, Chih-Tsun
李進福
Li, Jin-Fu
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2024
畢業學年度: 112
語文別: 英文
論文頁數: 36
中文關鍵詞: 憶阻器非線性脈衝神經網路
外文關鍵詞: memristor, non-linearity, spiking neural network
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  • 隨著神經網路應用的快速擴展,硬體運算需求不斷增加,用記憶體內運算(CIM)來改進的吞吐量和耗能成為了一種有前景的解決方案。這種方法通過在記憶體中直接進行計算,減少了處理器和記憶體之間數據傳輸的時間和耗能。尤其在非揮發性記憶體技術(如電阻式隨機存取記憶體(ReRAM))的發展,即時推論變得更加可行。ReRAM交叉陣列因其能夠在記憶體內進行大量點積操作且具有高效能和低功耗特性,成為深度神經網路推論加速的重要部分。然而,ReRAM的非理想性使得其內存計算容易出錯,這種特性限制了字線並行運算。為了提升性能並增加同時啟動的字線數量,提出了解決方法。

    這篇論文提出針對非線性電流累加做電流補償來校準,根據每周期輸入為一的數目去決定補償的多寡,並在ReRAM陣列每周期計算完後進行校準。為了模擬ReRAM陣列所考慮到電路上非理想的電流效應,與在SNN模型上所特有的運算方式,有和業界合作並提取相關電路資料來進行模擬,在準確率97%以上的模擬器上來進行結果的驗證與模擬。

    在經由補償校準後的方法,從模擬的結果來看,透過此方法可以增加相比以往將近4倍的加速,在正確率上也能達到98.35%,而且其面積增加不到1.03倍。


    As the rapid expansion of neural network applications continues, the demand for hardware computation is increasing. In-memory computing (CIM) emerges as a promising solution to improve throughput and energy efficiency. This approach reduces the time and energy consumption associated with data transfer between processors and memory by performing computations directly within the memory. The development of non-volatile memory technologies, such as resistive random access memory (ReRAM), has made instant inference more feasible. ReRAM crossbar arrays, due to their ability to perform a large number of dot product operations within the memory with high efficiency and low power consumption, have become an essential component in accelerating deep neural network inference. However, the non-ideal characteristics of ReRAM make in-memory computations prone to errors, which limits wordline-level parallelism. To enhance performance and increase the number of concurrently activated wordlines, solutions have been proposed.

    In this thesis, we proposes a calibration method for current compensation to address the nonlinear current accumulation. The compensation amount is determined based on the number of inputs equal to one in each cycle, and calibration is performed after each cycle of computation in the ReRAM array. To simulate the non-ideal current effects of the ReRAM array and the specific computation methods in the Spiking Neural Network (SNN) model, industry collaboration was conducted to extract relevant circuit data for simulation. The results were verified and simulated on a simulator with an accuracy of over 97%.

    The proposed current compensation and calibration method, based on simulation results, can achieve nearly a fourfold increase in acceleration compared to previous methods, with an accuracy of 98.35%. Additionally, the area increase is less than 1.03 times.

    1 Introduction 7 1.1 Objective and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Background 9 2.1 ReRAM array multiply accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 1T1R ReRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 ReRAM-based Neural Network Accelerator Architecture . . . . . . . . . . . . . . 12 2.4 Non-idealities of the ReRAM crossbar array . . . . . . . . . . . . . . . . . . . . . 12 3 ReRAM-based SNN Operation 15 3.1 Spiking Neural Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Memristor-Based Spiking Neural Network . . . . . . . . . . . . . . . . . . . . . . 15 4 Calibration for Non-linearity 18 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Analysis of Bitline Calculations in ReRAM Arrays . . . . . . . . . . . . . . . . . 18 4.3 Calibration for bitline current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.1 The magnification to be compensated . . . . . . . . . . . . . . . . . . . . 22 4.3.2 Compensation architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.3 Compensation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Experimental Results and Analysis 26 5.1 Experiment Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 The Calibration Correct Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 The Calibration Circuit Area Analysis . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Conclusions and Future Work 32 6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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