研究生: |
方瑋豪 Fang, Wei-Hao |
---|---|
論文名稱: |
應用於寬頻多輸入多輸出毫米波系統下傳通訊協議及混合式預編碼處理晶片設計 Downlink Communication Protocol and VLSI Design of Hybrid Precoding for Wideband Millimeter Wave MIMO Systems |
指導教授: |
黃元豪
Huang, Yuan-Hao |
口試委員: |
蔡佩芸
Tsai, Pei-Yun 陳喬恩 Chen, Chiao-En 蔡尚澕 Tsai, Shang-Ho |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 通訊工程研究所 Communications Engineering |
論文出版年: | 2019 |
畢業學年度: | 108 |
語文別: | 英文 |
論文頁數: | 90 |
中文關鍵詞: | 毫米波 、混合預編碼 、多輸入多輸出 、寬頻 、下傳 、正交多工 |
外文關鍵詞: | mmWave, Hybrid Precoding, MIMO, Wideband, downlink, OFDM |
相關次數: | 點閱:1 下載:0 |
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在下一世代行動通訊系統中,高吞吐量的傳輸方式是最基本的需求,而多輸入多輸出毫米波系統與大規模陣列天線可以滿足這樣的需求。然而,在全數位的陣列天線系統中,大量的射頻鏈與數位類比轉換器會消耗許多硬體資源,因此採用混合式預編碼架構來減少射頻鏈與數位類比轉換器。此外,正交分頻多工技術也被期許可以套用在頻率選擇性通道中。在這篇論文中,我們提出了一個下傳通訊協議。這個下傳通訊協議可以被分成三個階段,探測、回饋以及波束成形階段。量測階段時,基地台預估下傳通道資訊及計算預編碼器矩陣。在回饋階段時,移動端會獲得回饋的資訊以及計算組合器矩陣。在波束成形階段時,兩端的預編碼器矩陣及組合器矩陣都已完成,下傳通訊即可開始。此外,我們用TSMC 40NM CMOS實現了移動端的組合器處理器。類比組合器處理器可以運作在200 MHz的頻率下。功耗及吞吐量可以在Nr×NRF=4×4/ 8×8下,達到10.75/30.53 mW及0.71/0.21 M 矩陣/每秒。數位組合器處理器可以運作在200 MHz的頻率下。功耗及吞吐量可以在NRF×Ns=4×1/4×2/8×1/8×2/8×4下,達到8.41/16.12/23.31/36.99/78.06 mW及7.14/7.14/3.84/3.84/3.84 M 矩陣/每秒。
In the next-generation communication systems, high-throughput transmission is the essential necessity. The millimeter wave (mmWave) multiple-input and multiple-output (MIMO) system can provide high-throughput transmission. However, the RF chains and data converters in the fully-digital MIMO system cost a lot of hardware resources. As a result, hybrid precoding is adopted to reduce the cost of RF chains and data converters. Furthermore, orthogonal frequency division modulation (OFDM) is expected to be applied with frequency selective broadband channel. In this thesis, we propose a downlink communication protocol which is divided into three stages, sounding, feedback and beamforming stage. Base station (BS) estimates the downlink channel and calculate precoders at sounding stage. Mobile station (MS) obtains the feedback information and calculate combiners at feedback stage. Downlink communication is prepared at beamforming stage. In addition, we implement the proposed combiner processor with TSMC 40 nm CMOS process technology. The analog combining processor can operate with 200MHz clock speed. The power consumption are 10.75/30.53 mW and throughput can achieve 0.71/0.21 M matrices per second for Nr × NRF = 4× 4/8 × 8. The analog baseband processor can operate with 200MHz clock speed as well. The power consumption are 8.41/16.12/23.31/36.99/78.06 mW and normalized throughput can achieve 7.14/7.14/3.84/3.84/3.84 M matrices per second for NRF × Ns = 4× 1/4 × 2/8 × 1/8 × 2/8 × 4.
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