研究生: |
陳哲平 Chen, Che-Ping. |
---|---|
論文名稱: |
NAND型快閃記憶體胞間空隙對干擾、可靠度及耐久度之影響 Effect of Airgap Design on Interference, Reliability, Endurance in NAND Flash Memories |
指導教授: |
金雅琴
King, Ya-Chin |
口試委員: |
劉怡君
Liu, Yi-Chun 陳映仁 Chen, Ying-Jen |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 積體電路設計與製程開發產業碩士專班 Graduate Program in Integrated Circuit Design and Process Development |
論文出版年: | 2018 |
畢業學年度: | 106 |
語文別: | 中文 |
論文頁數: | 72 |
中文關鍵詞: | 胞間空隙 、干擾度 、可靠度 、耐久度 |
外文關鍵詞: | Airgap, Interference, Reliability, Endurance |
相關次數: | 點閱:4 下載:0 |
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近年來,隨著科技的進步,電子產品越來越普及,除了軟體與演算法的進步,硬體上的支援當然是不可或缺的,並需要有更大的儲存空間,用以支援軟體。無論是揮發式記憶體亦或是非揮發式記憶體絕對都在積體電路系上必須且重要的模組。搭配積體電路製程技術上的進步,得以達到元件尺寸微縮,使記憶體密度可以提高並有較大的儲存空間。然而,微縮尺寸的同時也帶來了許多挑戰,像是較大的漏電流、高電壓、高電場等,都需要進一步研究討論並提出解決方案。
目前,非揮發式記憶體又以快閃記憶體為現在的主流技術,本論文將討論NAND型快閃記憶體中胞間空隙對元件特性的影響。胞間空隙的設計,利用較低的介電常數,降低字元間的電容,以達到降低字元間干擾效應。本論文將研究討論的主軸分為兩部份,第一部分為藉由模擬,分析特性受到胞間空隙設計的影響,另一部分則以實際元件量測結果,了解結構設計如何造成對元件可靠度的變化。
透過元件模擬軟體,模擬不同胞間空隙大小對側向電場和直接電場所造成之影響,並搭配1X奈米NAND型快閃記憶體作為量測元件,利用不同厚度的氧化層,將具有不同大小的胞間空隙進行實際元件量測分析。
同時,研究胞間空隙所可能引發的各項優缺點加以分析與討論。另外,針對可靠度部分,主要探討為不同的胞間空隙大小對耐久度的影響,分別以三種比例的胞間空隙,進行寫入抹除循環的壓力測試,藉此分析其對循環壓力的耐久度,並發現次臨界擺幅與串接電阻亦會受到胞間空隙結構的影響。
With the advancement of technology, electronic products become more pervasive in our daily lives. Besides software and algorithm improvement, the improved hardware in electronic hardware, most ICs, are indispensable. We need bigger capacity in data storage to support more sophisticated software functions. Both volatile memory and non-volatile memory play important roles. Aggressive scaling of VLSI technologies enables higher data storage capacities in a much compact solid-state ICs. However, these advanced memories chip face several challenges as devices scale down, like larger leakage current, higher voltage, and higher electron field.
Nowadays, flash memory technology is a mainstream memory for data and code stored in portable electronics. Using lower dielectric constant make the capacitance in the word line are commonly used to reduce interference between adjacent cells on 2D NAND Flash cells.
In this thesis, the impact on airgap design on 2D NAND array is investigated by device simulation and actual measurement results on test samples with different airgap designs. Through device simulator, the influent of the direct field and fringe field with different airgap size can be clarified. Measurement data on 1X nm NAND Flash devices further provide evidence to support the effect on device reliability by samples with different air-gap structures. Degradation on the subthreshold swing and the string resistance due to cycling stresses are also found to depends slightly on air-gap structures.
[1] Wing-kei S. Yu, Ruirui Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh “SRAM-DRAM Hybrid Memory with Applications to Efficient Register Files in Fine-Grained Multi-Threading,” 2011 38th Annual International Symposium on Computer Architecture (ISCA),pp. 247 – 258,2011.
[2] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash memory cells-an overview, ” Proceedings.IEEE, pp. 1248 – 1271, vol. 85 , issue8, 1997.
[3] Pierpaolo Nicosia, Fulvio Nava, “Test Strategies on Non Volatile Memories, ” STMicroelectronics Flash Memory Group Italy. Proceedings. 22th IEEE, pp. 11-18,2007.
[4] Jan Peter van Zandwijk, Aya Fukami, “NAND Flash Memory Forensic Analysis and the Growing Challenge of Bit Errors,” Netherlands Forensic Institute, Proceedings. IEEE Security & Privacy, pp. 82-87, vol. 15 ,issue 6, 2017.
[5] Simon Tam, Ping-Keung Ko, Chenming Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s,” Proceedings. IEEE Transactions on Electron Devices, pp. 1116 - 1125, vol. 31, issue 9, 1984.
[6]Jae-Duk Lee, Jeong-Hyuk Choi, Donggun Park, Kinam Kim, “Degradation of Tunnel Oxide by FN Current Stress and ITS Effects,” 2003 IEEE International Reliability Physics Symposium Proceedings. 2003. 41st Annual., pp. 497 - 501, 2003.
[7] Air-Gap Application and Simulation Results for Low Capacitance in 60nm NAND Flash Memory, “Air-Gap Application and Simulation Results for Low Capacitance in 60nm NAND Flash Memory,” 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, pp. 54 - 55, 2007.
[8] Pieter Blomme, Chi Lim Tan, Laurent Souriau, Janko Versluijs, Geert Van Den Bosch, Jan Van Houdt, “Experimental study of programming saturation in low-coupling planar high-k/metal gate NAND Flash memory cells using a dedicated test structure,” 2014 IEEE 6th International Memory Workshop (IMW), pp. 1 - 4, 2014.
[9]Yi-Hsuan Hsiao, Hang-Ting Lue, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “A Study of Stored Charge Interference and Fringing Field Effects in Sub-30nm Charge-Trapping NAND Flash,” 2009 IEEE International Memory Workshop, pp. 1 - 2, 2009.
[10] YeonJoo Jeong, Sangjo Lee, Sunghoon Cho, Pyunghwa Kim, Milim Park, SungPyo Lee, Hyunyoung Shim, Myoung Kwan Cho, Kun-Ok Ahn, Gihyun Bae, Sungwook Park, “A Investigation of E/W Cycle Characteristicsfor 2y-nm MLC NAND Flash Memory Devices,” 2012 4th IEEE International Memory Workshop, pp. 1 - 3, 2012.
[11]ChangHyun Lee, Albert Fayrushin, Sunghoi Hur, Youngwoo Park, Jungdal Choi, Jeonghyuk Choi, Chilhee Chung, “Physical Modeling and Analysis on ImprovedEndurance Behavior of P-Type Floating Gate NANDFlash Memory,” 2012 4th IEEE International Memory Workshop, pp. 1 - 4, 2012.
[12]Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, Sheng-Chih Lai, Erh-Kun Lai, Shih-Ping Hong, Ming-Tsung Wu, F. H. Hsu, N. Z. Lien, Chi-Pin Lu, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “Understanding STI Edge Fringing Field Effect on the Scaling of Charge-Trapping (CT) NAND Flash and Modeling of Incremental Step Pulse Programming (ISPP),” 2009 IEEE International Electron Devices Meeting (IEDM), pp. 1 - 4, 2009.
[13]Hao-Chiao Hong, Long-Yi Lin, Chun-Jung Liu, “Design of an On-Scribe-Line 12-bit Dual-Slope ADC for Wafer Acceptance Test,” 2017 International Conference on Applied System Innovation (ICASI), pp. 1751 - 1754, 2017.
[14]Jae-Duk Lee, Sung-Hoi Hur, Jung-Dal Choi, “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, pp. 264 - 266, vol. 23, issue 5, 2002.
[15] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, T. Okazawa , “A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories,” Proceedings. IEEE International Electron Devices Meeting, pp. 19-22, 1993.
[16]Udayan Ganguly, Yoshitaka Yokota, Jing Tang; Shiyu Sun, Matt Rogers, Miao Jin, Kiran Thadani, Hiroshi Hamana, Garlen Leung; Balaji Chandrasekaran, Sunderraj Thirupapuliyur, Chris Olsen; Vicky Nguyen; Swami Srinivasan, “Scalability enhancement of FG NAND by FG shape modification”, Proceedings IEEE International Memory Workshop, pp.1-4,2010.
[17]Sang-ku Park, Seung-Hyun Kim, Sang-Ho Lee, Do-Bin Kim, Myung-Hyun Baek, Byung-Gook Park , “Interface and oxide trap analysis at tunnel oxide of NAND flash memory with excluding the effect of floating gate,” 2016 IEEE Silicon Nanoelectronics Workshop (SNW), pp. 90-91, 2016.
[18] T. H. Yeh, S. W. Lin, Y. J. Chen, K. F. Chen, J. S. Huang, C. H. Cheng, L. H. Chong, S. H. Ku, N. K. Zous, I. J. Huang, T. T. Han, M. S. Chen, W. P. Lu, K. C. Chen, Tahui Wang, Chih-Yuan Lu, “Gate Stack Etch induced Reliability Issues in Nitrided-based Trapping Storage Cells,” Proceedings. 2010 International Symposium on VLSI Technology, System and Application, pp. 48-49, 2010.