量子點細胞元自動化 (Quamtum-dot Cellular Automata) 在奈米技術上已經成為一種新的設計範例。由於在量子點細胞元自動化上的運算邏輯為多數邏輯，近年來已有許多關於多數邏輯電路的合成和優化的研究。在本論文中，我們對於一個表達多數邏輯電路的表示法：多數反相圖，提出一個合併節點的優化方法以減少電路的面積。我們的方法不須使用可滿足性問題求解器，而是利用邏輯蘊含技巧辨識出合併的節點。我們利用EPFL之測試電路進行實驗，其結果顯示當我們的方法與最新的方法結合使用後，平均可以減少21%之節點個數。

Quantum-dot Cellular Automata (QCA) has emerged as a new design paradigm for nanotechnologies. Since the operational logic in QCA is the majority logic, much research about the synthesis and optimization of majority logic has been proposed recently. In this thesis, we propose an optimization method by merging nodes in the Majority-Inverter-Graph, which is the representation of majority logic circuits. Instead of using satisfiability solvers, our approach can identify the node mergers by using logic implications for circuit size reduction. The experimental results show that for a set of EPFL benchmarks, our approach can minimize the node count by 21% when integrated with the state-of-the-art on average.

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http://lsi.epfl.ch/MIG