在快閃記憶體的電路核心中，能隙參考電壓電路(bandgap reference circuit)和字線解碼電路(Wordline decoder)是其中兩個重要的部份。能隙參考電壓電路可以提供了較外界供應電壓更準確的電壓，而其受溫度的影響也較小。它可以經由比較電路應用於提供準確的讀(read)、抹(erase)、寫(write)電壓，使記憶體元件的讀(read)、抹(erase)、寫(write)更能準確地控制。而字線解碼電路則是應用於將讀、抹、寫操作時，所需要的各種不同高、低電壓傳至記憶體元件陣列的字線。
為了與邏輯製程相容以製作嵌入式快閃式記憶體(embedded flash memory)。本篇論文提出了在單井製程的限制下，這兩種電路的實現方法。首先在能隙參考電壓電路中，由於此種單井製程並未對BJT的特性有很好的掌握，使得輸出電壓的準確度不能夠準確的掌握。故新型電路去除掉BJT的使用，使得每一個電路在製作出來之後可以免除掉BJT特性的變化，而造成參考電壓的大變化。此亦簡化了設計的困難度。

而在字線解碼電路方面，因為在單井製程下NMOS的端點無法耐高電壓，但為了提供0V的電壓，NMOS是必須採用的。且由於在邏輯製程中，閘極到通道崩潰電壓(Gate to Channel Breakdown Voltage)亦小於寫入時所需的高電壓。在此種限制下，新型電路提供了新的電路組態，並在製程限制下，使用一新型可耐端點高電壓的NMOS，達到字線解碼電路的正常操作，並保留直流耗電為0的低耗電特性。

In peripheral circuits of flash memory, bandgap reference circuit and wordline decoder are two very important components. Bandgap reference circuit provides precise and stable voltage level under temperature and power supply variations. It provides accurate voltages for read, erase and program through compare circuit so that the memory operation can be precisely controlled. Wordline decoder is used to transmit various voltages to the wordline for read, erase or write of a memory cell.
This paper provides newly design for bandgap reference circuit and wordline decoder circuit for embedded flash memory in standard logic CMOS process. Because BJT characteristics are not optimized and well controlled in CMOS process, all-MOSFET configuration without BJT is employed in the new proposed voltage reference circuit. This all-MOSFET voltage reference circuit demonstrates comparable characteristics to conventional BJT bandgap reference circuits.

Using standard logic process for embedded flash memory fabricated, voltages across source/drain junctions and gate to channel are limited to VDD. The new wordline decoder circuit uses cascode configuration that releases the voltage across device terminals and provide sufficient operation voltages. This circuit has been successfully fabricated and tested.

[1] W. Johnson, G. Perlegos, A. Renninger, G. Kuhn, and T. Ranganath “A 16k bit electrically erasable non-volatile memory,” in Tech. Dig. IEEE ISSCC, p.152, 1980
[2] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro and S. Tanaka, “A new Flash EEPROM cell using triple polysilicon technology,” in IEDM Tech. Dig., p.464-p.467, 1984
[3] S. Mukherjee, T. Chang, R. Pang, M. Knecht and D. Hu, “A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM,” in IEDM Tech. Dig., p.616-p.619, 1985
[4] 徐清祥及沈士傑, “快閃式記憶體結構及其操作模式”
[5] R. Kazerounian and B. Eitan, “A single-poly EPROM for custom CMOS logic applications”, IEEE Custom Integrated Circuits Conference, p.59-p.62, 1985
[6] M. Chi and A. Bergemont, “A new single-poly Flash Memory Cell with low-voltage and low-power operations for embedded applications”, Device Research Conference Digest, 1997. 5th , 1997 Page(s): 126 –127
[7] Song Liu and R.J. Baker, “Process and Temperature Performance of a CMOS Beta-Multiplier Voltage Reference”, Midwest Symposium on , 1999 P. 33-36
[8] Luiz Vermaas , “A Bandgap Voltage Reference Using Digital CMOS Process”, IEEE , 1998 P. 303-306