研究生: |
蔡志忠 Chih-Chung Tsai |
---|---|
論文名稱: |
橫向高電壓碳化矽PN二極體與金氧半場效電晶體之特性模擬與分析 Simulation of Lateral High Voltage SiC PN Diodes and MOSFETs |
指導教授: |
黃智方
Chih-Fang Huang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 中文 |
論文頁數: | 104 |
中文關鍵詞: | 碳化矽 、PN 二極體 、金氧半場效電晶體 、超級接面 、高功率 、半絕緣體 |
外文關鍵詞: | SiC, PN Diodes, MOSFETs, Superjunction, High power, Semi-insulating |
相關次數: | 點閱:3 下載:0 |
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本篇論文提出並模擬一個新穎橫向高電壓PN二極體結構,元件的設計理念為透過超接面的原理,使得此橫向功率元件的導通電阻降低同時提高了崩潰電壓。並且利用碳化矽良好的材料特性,期望元件有良好的電流電壓特性。模擬結果顯示透過基底為semi-insulating,元件的特性接近主要載子元件,其結果是較高且隨溫度而增加之正向導通電壓,並且使得其動態的反向回覆特性遠優於有少數載子儲存效應的PiN二極體。設計崩潰電壓為3560V的4H型橫向高電壓PN二極體,其導通電阻(Ron,sp)為32.5mΩ-cm2,VB2/Ron約為390 MW/cm2,和文獻中其他4H型垂直蕭基二極體的效能相當,並且展現超越目前橫向碳化矽高電壓MOSFETs的效能。
當橫向高電壓PN二極體與MOSFETs結構做結合時,形成一個橫向高電壓MOSFETs,此結構的耐壓主要是由橫向PN二極體的漂移區的超接面設計所承受,在橫向MOSFETs與橫向PN二極體有相同的設計下時,預計兩者會有相近的崩潰電壓。而此橫向MOSFETs的導通電阻約為0.16 Ω-cm2,同時在汲極電壓極低的範圍內會有電壓偏移量的情況,透過改變通道與漂移區接面的位置可以有效地降低此偏移量的發生。
In this paper, we propose and simulate a novel lateral silicon carbide (SiC) high voltage PN diode structure. These devices employ the superjunction principle to reduce the specific on-resistance and to enhance the blocking voltage (BV). Through the excellent material characteristics of SiC the devices are expected to have good IV characteristics. The simulation results show that the lateral SiC high voltage diodes behave similar to majority carrier devices which the specific on-resistance rises with increasing temperature and the reverse recovery is better than convention PiN diodes due to the devices fabricated on semi-insulating substrate. The specific on-resistance of a 3500V lateral 4H-SiC diode is 32.5mΩ-cm2. The Baliga Figure of Merit (BFOM) is 390 MW/cm2, comparable to the 4H-SiC Schottky diodes and superior to the 4H-SiC lateral MOSFETs in the literature.
The lateral high voltage PN diodes are combined with lateral MOSFETs to form the lateral high voltage MOSFETs which have the same blocking ability with lateral PN diodes when these two devices have close BV designs. The simulation results show that the lateral MOSFETs have a specific on-resistance 0.16Ω-cm2, and an offset near drain to source voltage is near to zero. This offset problem can be solved through controlling drift region etching depth.
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