隨著網路應用的日益成長，新的網路管理設備相繼產生，如入侵防禦系統(IPS)及防火牆(Firewall)。然而，伴隨著網路頻寬倍數於處理器(CPU)計算速度的快速成長，即使以現有最高效能的單一處理器仍無法即時處理龐大的網路資料流量。為了要使網路設備不成為整個的網路瓶頸，許多系統設計師選擇在對稱式多處理器平台(SMP)上進行研發網路設備，期許經由倍數化處理器數量來提升系統效能。然而，隨著處理器數量的增加，許多技術上的瓶頸相繼出現，增加了開發系統的難度以及延長了開發時間。如何克服這些瓶頸並且將網路流量有效率的平均分配到每一顆處理器上成為了重要的議題。
這篇論文主要在提出一個新的系統架構，適用於所有網路管理設備。我們提出了以多層的負載平衡器(Load balancers)來平均分派網路流量到不同的處理器進行運算，同時保持相同連線內的封包先後順序。為了要降低多處理器內Locking機制所帶來的系統負擔，並增加cache的一致性，我們提出Locking-Free的架構，藉由這樣的架構來簡化系統開發的難度。並且提出Early Filtering的機制，藉由快速處理Layer 3封包，來提升整體效能以及降低記憶體使用。隨著處理器數目的增加，更能突顯我們架構的優越性。在經由現實封包的模擬以及驗證下，實驗結果證實了我們的架構可以大幅的提升系統效能，平均化處理器使用率並簡化網路設備開發的流程。

The continuing Internet bandwidth explosion and the advent of new applications have created great challenges for network forwarding devices, e.g., IPS and Firewall. With network bandwidth doubling about twice as fast as CPU performance, the problem shows. Consequently, more and more systems designers are choosing to distribute the workload across multiple CPUs, using symmetric multi-processing (SMP). Workload distribution is critical to the performance of SMP architecture.
This thesis introduces a novel system to balance the scheduled traffic over multiple processing cores maintaining in-order service. We present a multi-layered load-balancer which provides higher performance and better distribution as number of processors increases. Also, we introduce early filtering mechanism which can higher system performance, decrease memory usage and lower packet latency. Based on measurements of Internet traffic, the simulation results show that our mechanism provides lower average delay and better workload distribution compared with other load-balancing system.

References
[1] Broadcom ASIC solutions, http://www.broadcom.com/products/Enterprise-Networking/ASICs
[2] Realtek communication SOCs, http://www.realtek.com.tw/products
[3] Intel Network Processors For Communications and Networked Embedded Applications, http://www.intel.com/design/network/products/npfamily/index.htm?iid=ncdcnav2+proc_netproc&
[4] Port-Well IPC products, http://www.portwell.com.tw/products/ipc_index.php
[5] Tyan Platform, http://www.tyan.com/products/products.html
[6] Multi-Core Processors -The Next Evolution in Computing, http://multicore.amd.com/GLOBAL/WhitePapers/Multi-Core_Processors_WhiteThesis.pdf
[7] Discovering Multi-Core: Extending the Benefits of Moore's Law, http://www.intel.com/technology/magazine/computing/multi-core-0705.pdf
[8] David A. Patterson, John L. Hennessy," Computer Organization and Design: The Hardware/Software Interface, Third Edition"; Morgan Kaufmann
[9] David Culler, J.P. Singh, Anoop Gupta, "Parallel Computer Architecture: A Hardware/Software Approach"; Morgan Kaufmann
[10] Van Jacobson, “Berkeley TCP Evolution From 4.3-Tahoe to 4.3-Reno,” in Proceedings of the British Columbia Internet Engineering Task Force, July 1990.
[11] Lawrence Brakmo, Sean O’Malley, and Larry Peterson, “TCP Vegas: New Techniques for Congestion Detection and Avoidance,” in ACMSIGCOMM94, 1994.
[12] M. Bjorkman and P. Gunningberg. “Locking effects in multiprocessor implementations of protocols”. In ACM SIGCOMM Symposium on Communications Architectures and Protocols, 1993.
[13] A. Gupta, A. Tucker, and S. Urushibara. “The impact of operating system scheduling policies and synchronization methods on the performance of parallel applications”. In Proceedings of the 1991 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pp. 120-132, San Diego, CA, May 1991.
[14] A. Foong, J. Fung and D. Newell. “An In-depth Analysis of the Impact of Processor Affinity on Network Performance”. In IEEE Intl. Conference on Networks, Nov 2004.
[15] J. Salehi, J. Kurose and D. Towsley, "The effectiveness of affinity-based scheduling in multiprocessor network protocol processing", IEEE/ACM Trans. on Networking, vol. 4:4, pp. 516-530, 1996.
[16] FUJITSU Technical Information, http://www.labs.fujitsu.com/en/techinfo/linux/lse-0211/lse-0211.pdf
[17] USC/ISI, “Internet Protocol – Specification,” RFC 791, Sept. 1981.
[18] International Organization for Standardization, “Information Processing Systems—Data Communication High-Level Data Link Control Procedure—Frame Structure,” ISO 3309, Oct. 1984.
[19] Cao Z, Wang Z, Zegura E. “Performance of hashing-based schemes for Internet load balancing”. In: Nokia FB, ed. Proc. of the IEEE INFOCOM 2000. Piscataway: IEEE Computer and Communications Societies, pp. 332-341, 2000.
[20] Kornaros, G.; Orphanoudakis, T.; Zervos, N. “An efficient implementation of fair load balancing over multi-CPU SOC architectures”; Digital System Design, pp. 197–203, Proceedings Euromicro Symposium on 1-6 Sept. 2003.
[21] Kencl, L.; Le Boudec, J.-Y. “Adaptive load sharing for network processors”; INFOCOM 2002. Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings IEEE vol. 2, pp. 23-27, June 2002.
[22] Gero Dittmann, Andreas Herkersdorf. “Network Processor Load Balancing for High-Speed Links”; Proceedings of the SPECTS 2002.
[23] Luo, Y.; Laxmi Narayan Bhuyan; Chen, X. “Shared memory multiprocessor architectures for software IP routers”; Parallel and Distributed Systems, IEEE Transactions on vol. 14:12, pp.1240-1249, Dec. 2003.
[24] Weiguang Shi; MacGregor, M.H.; Gburzynski, P. “Load Balancing for Parallel Forwarding”; Networking, IEEE/ACM Transactions on vol. 3:4, pp791-801, Aug. 2005.
[25] Xinidis, K.; Charitakis, I.; Antonatos, S.; Anagnostakis, K.G.; Markatos, E.P. “An active splitter architecture for intrusion detection and prevention”; Dependable and Secure Computing, IEEE Transactions on vol. 3:1, pp.31-44, Jan.-March 2006.
[26] Bart Haagdorens, Tim Vermeiren and Marnix Goossens, "Improving the Performance of Signature-Based Network Intrusion Detection Sensors by Multi-threading"; WISA 2004, LNCS 332