積體電路的佈局在晶片設計的過程中是非常重要的步驟，佈局的好壞直接影響到面積、可繞性與晶片效能。因此在過去有許多針對佈局的相關研究，在深次微米時代，高晶片複雜度、多層繞線材質以及wire delay 重要性的增加，使得我們必須正視並解決隨之而來的各種問題，因此在本篇論文中，我們提出一個效能導向的積體電路佈局最佳化系統。這系統包含以下三個部分，第一部分是一個基於力平衡方法來達到效能導向目的的標準元件佈置方法，第二部分是一個三階段的繞線前置處理方法，第三部份則為一個多層的連接單元最佳化方法。以下會針對這三個部分做一說明。
在本論文的第一部份我們提出一個效能導向的標準元件佈置方法，這個方法主要是採用力平衡的原理。在我們的模型裡，對於每一條重要訊號路徑，我們都會加上一條虛擬鏈結來強調其重要性。本方法的概要內容如下：給定輸出入埠的位置以及 floorplan 的資訊，我們輪流移動元件到其力平衡的位置直到達成整體的平衡狀態，然後擺放佈局空間的最上面和最下面一列，接著再對剩下的元件做力平衡的步驟，然後擺放最上和最下一列，如此重複進行直到所有的佈局空間都放置完成為止。

在本論文的第二部分我們建構了一個繞線前置處理器，這個前置處理的方法分為三個階段，在第一個階段我們針對每一條 net建構一個效能最佳化導向的繞線樹，在第二個階段我們將繞線樹的線段配置於二維的繞線軌道上，最後我們將所有未連接的部分連接起來以完成整個繞線的步驟。我們成功地將這個前置處理方法整合到業界的晶片設計流程上。

在最後一個部分我們提出一個新的多層繞線層指定演算法來降低連接單元數目以進一步的改善佈局的品質。我們將多層連接單元數目最小化問題轉換成一個對應的多方向圖形分割問題，並且考慮到佈局時的實際限制。同時我們也將 crosstalk 的問題列入考慮。我們提出一個以模擬煉鐵法為基礎的演算法來解決這個問題。實驗顯示我們的方法可以明顯地降低連接單元的數目或是 crosstalk 的影響。

We study the layout optimization problem of integrated circuit design. First, we propose a performance-driven cell placement method based on a modified force-directed approach. After that, we utilize a 3-step preprocessing approach for whole chip detail routing. Finally, we develop a k-layer constrained via minimization algorithm.
Placement and routing are two important steps in physical design of very large scale integrated circuits. They significantly affect layout area, routability and performance. Standard-cell-based layout style is very popular for semi-custom design because it enables the success of both synthesis methodology and automatic placement and route (APR) flow. In the past, many approaches have been proposed to optimize the layout quality via placement or routing process.

In the very deep submicron era, large chip complexity, multiple metal layer, and wire delay dominance together call for re-investigation of these current solutions. Therefore, we implement a layout optimization system to achieve the timing-driven objective for very deep submicron design. We integrate our system into an industry design flow to evaluate the efficiency and effectiveness of our approaches.

In the first part, we design a modified force-directed algorithm to perform timing-driven placement. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given a user-specified I/O pad locations at the chip boundary and starting with all core cells in the chip center, we iteratively move a cell to its force-balanced location assuming all other cells are fixed. The process stops when no cell can be moved farther than a threshold distance. Next, cell rows are adjusted one at a time starting from the top and bottom. After forming theses two rows (top/bottom), all movable core cells' force-balanced locations are updated. The row-formation-and-update process continues until all rows are adjusted and, hence, a legal placement is obtained. We also study the effect on both layout quality and CPU time consumption due to the amount of pseudo net added. We found that the introduction of pseudo net indeed significantly improves the layout quality.

The next part is a preprocessor for a router. We propose a 3-step approach for net planning. In the first step, we construct a performance-driven Steiner tree for each net ignoring the existence of other nets. In the second step, we optimally assign significant wire segments of all trees to tracks of a two-dimensional, two-layer grid. Finally, in the third step, we complete the remaining local short connection between net terminals and those assigned wire segments and resolve any violations or congestion. We have incorporated this approach into an industrial VDSM design flow.

Finally, we employ a new layer assignment approach for the k-layer constrained via minimization (k-CVM) to improve the layout quality further. We transform the k-CVM problem into a constrained k-way graph partitioning one. Practical issues such as pin-out constraint, over-the-cell constraint, and overlapping between wire segments of the same net, have all been taken into consideration. We also address the crosstalk issue. We propose a simulated-annealing based algorithm for this problem. A set of large routing results generated by a commercial four-layer router has been used to test the effectiveness of the program. This work is the first to demonstrate the feasibility of via minimization for practical-sized multi-layer layout.

[1] K. Ahn and S. Sahni, ‘‘Constrained via minimization,’’ IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, pp. 273-282, February 1993.
[2] K. J. Antreich, F. M. Johannes, and F. H. Kirsch, ‘‘A new approach for solving the placement problem using force models,’’ Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 481-486, 1982.
[3] H. B. Bakoglu, ”Circuits, Interconnections, and Packaging for VLSI,’’ Addison-Wesley, 1990.
[4] F. Barahona, ‘‘On via minimization,’’ IEEE Transactions on Circuits and Systems, 37(4):527-530, April 1990.
[5] E. Barke, ‘‘Line-to-ground capacitance calculation for VLSI: A comparison,’’ IEEE Transactions on Computer-Aided Design, vol. 7, pp. 295-298, February 1988.
[6] M. A. Breuer, ‘‘A class of min-cut placement algorithms,’’ Proceedings of Design Automation Conference, pp. 284-290, 1977.
[7] M. A. Breuer, ‘‘Min-cut placement,’’ Journal of Design Automation and Fault-Tolerant Computing, pp. 343-382, Oct. 1977.
[8] F. Brglez, D. Bryan, K. Kozminski, ‘‘Combinational Profiles of Sequential Benchmark Circuits,’’ International Symposium on Circuits and Systems, pp. 1929-1934, 1989.
[9] S. Burman, H. Chen and N. Sherwani, ‘‘Improved global routing using λ-geometry,’’ Proceedings of 29th Annual Allerton Conference on Communications, Computing, and Controls, October 1991.
[10] H. Chan, P. Mazumder, and K. Shahookar, ‘‘Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome,’’ Integration: the VLSI Journal, vol. 12(1), pp. 49-77, November 1991.
[11] C. C. Chang and Jason Cong, ‘‘An efficient approach to multi-layer layer assignment with application to via minimization,’’ Proceedings of the 34th ACM/IEEE Design Automation Conference, 1997.
[12] K. C. Chang and D. H. Du, ‘‘Efficient algorithms for layer assignment problem,’’ IEEE Transactions on Computer-Aided Design, CAD-6(1):67-78, January 1987.
[13] K. C. Chang and D. H. Du, ‘‘Layer assignment problem for three-layer routing,’’ IEEE Transactions on Computers, vol. 37, no. 5, pp. 625-632, May 1988.
[14] K. Chaudhary, A. Onozawa, and E. S. Kuh, ‘‘A spacing algorithm for performance enhancement and cross-talk reduction,’’ Proceedings of International Conference on Computer-Aided Design, pp. 697-702, November 1993.
[15] H. H. Chen, and C. K. Wong, “Wiring and crosstalk avoidance in multi-chip module design,” Proceedings of Custom Integrated Circuits Conference, pp. 28.6.1-28.6.4, 1992.
[16] Lillis Cheng and Lin Ho, ‘‘New performance driven routing technologies with explict area/delay tradeoff and simultaneous wire sizing,’’ in Proceedings of 33rd Design Automation Conference, pp. 395-400, 1996.
[17] C. Chiang, M. Sarrafzadeh and C. K. Wong, ‘‘A powerful global router: Based on Steiner min-max trees,’’ Proceedings of IEEE International Conference on Computer-Aided Design, pp. 2-5, 1989.
[18] M. J. Ciesielski and E. Kinnen, ‘‘An optimum layer assignment for routing in IC’s and PCB’s,’’ Proceedings of 18th ACM/IEEE Design Automation Conference, pp. 733-737, 1981.
[19] J. P. Cohoon and P. L. Heck, ‘‘Beaver: A computational geometry based tool for switchbox routing,’’ IEEE Transactions on Computer-Aided Design, vol. 7, pp. 684-697, June 1988.
[20] J. P. Cohoon and W. Paris, ‘‘Genetic placement,’’ Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 422-425, 1986.
[21] J. Cong, K. S. Leung and D. Zhou, ‘‘Performance-driven interconnect design based on distributed RC delay model,’’ in Proceedings of Design Automation Conference, pp. 606-611, 1993.
[22] J. Cong and C. L. Liu, ‘‘Over-the-cell channel routing,’’ IEEE Transactions on Computer Aided Design, pp. 408-418, 1990.
[23] J. Cong, D. F. Wong and C. L. Liu, ‘‘A new approach to the three-layer channel routing problem,’’ Proceedings of IEEE International Conference on Computer-Aided Design, pp. 378-381, 1987.
[24] W. M. Dai, R. Kong, J. Jue, and M. Sato, “Rubber band routing and dynamic data representation,” Proceedings IEEE/ACM International Conference on Computer Aided Design, pp. 52-55, 1990.
[25] D. N. Deutsch, ‘‘A dogleg channel router,’’ Proceedings of 13th ACM/IEEE Design Automation Conference, pp. 425-533, 1976.
[26] A. E. Dunlop and B. W. Kerninghan, ‘‘A procedure for placement of standard-cell VLSI circuits,’’ IEEE Transactions on Computer Aided Design, pp. 92-98, Jan. 1985.
[27] Hans Eisenmann and Frank M. Johannes, ‘‘Generic Global Placement and Floorplanning,’’ Proceedings of the 35th Design Automation Conference, pp. 269-274, 1998.
[28] R. J. Enbody and H. C. Du, ‘‘Near-optimal n-layer channel routing,’’ Proceedings of 23rd ACM/IEEE Design Automation Conference, pp. 708-714, June 1986.
[29] S. C. Fang, K. E. Chang, W. S. Feng and S. J. Chen, ‘‘Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems,’’ Proceedings of the 28th IEEE/ACM Design Automation Conference, pp. 60-65, 1991.
[30] C. M. Fiduccia and R. M. Mattheyses, ‘‘A linear-time heuristic for improving network partitions,’’ Proceedings of the 19th Design Automation Conference, pp. 241-247, 1982.
[31] T. Gao and C. L. Liu, “Minimum crosstalk channel routing,” Proceedings of International Conference on Computer Aided Design, pp. 692-696, 1993.
[32] T. Gao, and C. L. Liu, ‘‘Minimum crosstalk channel routing,’’ IEEE Transactions on Computer-Aided Design, vol. 15, no. 5, pp. 465-474, May 1996.
[33] S. H. Gerez, “Algorithms for VLSI Design Automation,” John Wiley & Sons, 1999.
[34] A. K. Goel, ‘‘High-Speed VLSI Interconnections, Modeling, Analysis & Simulation,’’ John Wiley & Sons, 1994.
[35] G. Gudmundsson and S. Ntafos, ‘‘Channel routing with superterminals,’’ Proceedings of 25th Allerton Conference on Computing, Control and Communication, pp. 375-376, 1987.
[36] K. M. Hall, ‘‘An r-dimensional quadratic placement algorithm,’’ Management Science, 17:219-229, November 1970.
[37] M. Hanan and J. M. Kurtzberg, ‘‘Placement techniques,’’ Design Automation of Digital Systems, M. A. Breuer, Ed. Prentice-Hall Inc, pp. 213-282, 1972.
[38] A. Hashimoto and J. Stevens, ‘‘Wire routing by optimization channel assignment within large apertures,’’ Proceedings of the 8th Design Automation Workshop, pp. 155-163, 1971.
[39] L. He, C. K. Koh, D. Z. Pan, X. Yuan and J. Cong, “TRIO: A Tree, Repeater and Interconnect Optimization Package,” http://cadlab.cs.ucla.edu/~trio.
[40] J. Heisterman and T. Lengauer, ‘‘The efficient solution of integer programs for hierarchical global routing,’’ IEEE Transactions on Computer-Aided Design, vol. 10(2), pp. 204-211, February 1991.
[41] D. W. Hightower, ‘‘A solution to the line routing problem on a continuous plane,’’ Proceedings of 6th Design Automation Workshop, 1969.
[42] J. M. Ho, G. Vijayan and C. K. Wong, ‘‘A new approach to the rectilinear Steiner tree problem,’’ IEEE Transactions on Computer-Aided Design, vol. 9(2), pp. 185-193, February 1985.
[43] C. P. Hsu, ‘‘General river routing algorithm,’’ Proceedings of 20th ACM/IEEE Design Automation Conference, pp. 578-583, June 1983.
[44] K. S. Jhang, S. Ha, and C. S. John, ‘‘COP: A Crosstalk Optimizer for gridded channel routing,’’ IEEE Transactions on Computer-Aided Design, vol. 15, no. 4, pp. 424-429, April 1996.
[45] Y. Kajitani, ‘‘On via hole minimization of routing in a 2-layer board,’’ Proceedings of IEEE International Conference on Circuits and Computers, pp. 295-298, June 1980.
[46] B. W. Kernighan and S. Lin, ‘‘An efficient heuristic procedure for partitioning graphs,’’ Bell System Technical Journal, vol. 49, pp. 291-307, Feb. 1970.
[47] S. Kirkpatrick Jr., C. Gelatt, and M. Vecchi, ‘‘Optimization by simulated annealing,’’ Science, pp. 220(4598):489-516, May 1983.
[48] J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, ‘‘GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization,’’ IEEE Transactions on Computer Aided Design, vol. 10(3), pp. 355-365, 1991.
[49] Y. S. Kuo, T. C. Chern, and W. Shih, ‘‘Fast algorithm for optimal layer assignment,’’ Proceedings of 25th ACM/IEEE Design Automation Conference, pp. 554-559, 1988.
[50] Pran Kurup and Taher Abbasi, ‘‘Logic Synthesis Using Synopsys,’’ Second Edition, Kluwer Academic Publishers, 1998.
[51] C. Y. Lee, ‘‘An algorithm for path connections and its applications,’’ IRE Transactions on Electronic Computers, 1961.
[52] Jens Lienig, “A Parallel Genetic Algorithm for Performance-Driven VLSI Routing,” IEEE Transactions on Evolutionary Computation, vol. 1, no. 1, pp. 29-39, April 1997.
[53] John Lillis and Premal Buch, ‘‘Table-lookup methods for improved performance driven routing,’’ in Proceedings of 35th Design Automation Conference, pp. 368-373, 1998.
[54] W. K. Luk, ‘‘A greedy switchbox router,’’ Integration, The VLSI Journal, vol. 3, pp. 129-149, 1985.
[55] K. Mikami and K. Tabuchi, ‘‘A computer program for optimal routing of printed circuit connectors,’’ IFIPS Proceedings, H47:1475-1478, 1968.
[56] Fan Mo, Abdallah Tabbara and Robert, K. Brayton, ‘‘A Force-Directed Macro-Cell Placer,’’ Proceedings of the IEEE International Conference on Computer Aided Design, 4A.3, 2000.
[57] T. Ohtsuki, ‘‘Partitioning, Assignment and Placement,’’ North-Holland, 1986.
[58] A. Onozawa, ‘‘Layout compaction with attractive and repulsive constraints,’’ Proceedings of the 27th IEEE/ACM Design Automation Conference, pp. 369-376, June 1990.
[59] R. Y. Pinter, ‘‘Optimal layer assignment for interconnect,’’ Proceedings of IEEE International Conference on Circuits and Computers, pp. 398-401, September 1982.
[60] B. Preas and M. Lorenzetti, ‘‘Physical Design Automation of VLSI Systems,’’ The Benjamin Cummings Publishing Company, Inc., 1988.
[61] N. R. Quinn, ‘‘The placement problem as viewed from the physics of classical mechanics,’’ Proceedings of the 12th Design Automation Conference, pp. 173-178, 1975.
[62] S. M. Sait, and H. Youssef, “VLSI Physical Design Automation, Theory and Practice,” World Scientific, 1999.
[63] L. A. Sanchis, ‘‘Multi-way network partitioning,’’ IEEE Transactions on Computer, vol. 38, pp. 62-81, Jan. 1989.
[64] M. Sarrafzadeh and M. Wang, ‘‘NRG: Global and Detailed Placement,’’ Proceedings of IEEE International conference on Computer Aided Design, November 1997.
[65] Prashant Saxena and C. L. Liu, ‘‘A postprocessing algorithm for crosstalk- driven wire perturbation,’’ IEEE Transactions on Computer-Aided Design, vol. 19, no. 6, pp. 691-702, June 2000.
[66] C. Sechen and K. W. Lee, ‘‘ An improved simulated annealing algorithm for row-based placement,’’ Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 478-481, 1987.
[67] C. Sechen and A. Sangiovanni-Vincentelli, ‘‘The Timber Wolf placement and routing package,’’ IEEE Journal of Solid-State Circuits, Sc-20, pp. 510-522, 1985.
[68] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, ‘‘SIS: A System for Sequential Circuit Synthesis,’’ Memorandum No. UCB/ERL M92/41, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, May 1992.
[69] K. Shahookar and P. Mazumder, ‘‘A genetic approach to standard cell placement using meta-genetic parameter optimization,’’ IEEE Transactions on Computer Aided Design, pp. 500-511, May 1990.
[70] K. Shahookar and P. Mazumder, ‘‘VLSI cell placement techniques,’’ ACM Computing Surveys, 23(2), pp. 143-220, June 1991.
[71] Naveed A. Sherwani, “Algorithms for VLSI Physical Design Automation,” 3rd Ed., Kluwer Academic Publishers, 1999.
[72] N. Sherwani, S. Bhingarde, and A. Panyam, ‘‘Routing in The Third Dimension: From VLSI Chips to MCMs,’’ IEEE Press, 1995.
[73] H. Shin and A. Sangiovanni-Vincentelli, ‘‘Mighty: a rip-up and reroute detailed router,’’ Proceedings of IEEE International Conference on Computer-Aided Design, pp. 2-5, 1986.
[74] J. Soukup, ‘‘Fast maze router,’’ Proceedings of 15th ACM/IEEE Design Automation Conference, pp. 100-102, 1978.
[75] K. R. Stevens and W. M. VanCleemput, ‘‘Global via elimination in generalized routing environment,’’ Proceedings of International Symposium on Circuits and Systems,’’ pp. 689-692, 1979.
[76] W. J. Sun and C. Sechen, ‘‘A Loosely Coupled Parallel Algorithm for Standard Cell Placement,’’ Proceedings of IEEE International Conference on Computer Aided Design, pp. 137-144, 1994.
[77] T. G. Szymanski, ‘‘Dogleg channel routing is np-complete,’’ IEEE Transactions on Computer Aided Design, CAD-4, pp. 31-41, January 1985.
[78] S. Thakur, K. Y. Chao, and D. F. Wong, ‘‘An optimal layer assignment algorithm for minimizing crosstalk for three layer VHV channel routing,’’ IEEE International Symposium on Circuits and Systems, vol. 1, pp. 207-210, May 1995.
[79] Too-Seng Tia and C. L. Liu, ‘‘A New Performance Driven Macro-Cell Placement Algorithm,’’ Proceedings of EURO-DAC’93, pp. 66-71, 1993.
[80] Maogang Wang, Xiaojian Yang and Majid Sarrafzadeh, ‘‘Dragon 2000: Fast Standard-Cell Placement for Large Circuits,’’ Proceedings of the IEEE International Conference on Computer Aided Design, 6A.2, 2000.
[81] Joon-Seo Yim and Chong-Min Kyung, ‘‘Reducing cross-coupling among interconnect wires in deep-submicron datapath design,’’ in Proceedings of Design Automation Conference, pp. 485-490, 1999.
[82] Hai Zhou and D. F. Wong, ‘‘Global routing with crosstalk constraints,’’ in Proceedings of 35th Design Automation Conference, pp. 374-377, 1998.
[83] Y. Ogawa, M. Pedram, and E. S. Kuh, “Timing-driven placement for general cell layout,” Proceedings of IEEE International Symposium on Circuits and Systems, pp. 872-876, 1990.
[84] A. Srinivasan, K. Chaudhary, and E. S. Kuh, “RITUAL: A performance-driven placement algorithm,” IEEE Transactions on Circuits and Systems, vol. 39, no. 11, November, 1992.
[85] S. L. Ou, and M. Pedram, “Timing-driven placement based on partitioning with dynamic cut-net control”, Proceedings of 37th Design Automation Conference, pp. 472-476, 2000.
[86] S. W. Hur and J. Lillis, ‘‘Mongrel: Hybrid Techniques for Standard Cell Placement,’’ in Proc. of International Conference on Computer-Aided Design, pp. 165-170, 2000.
[87] K. Zhong and S. Dutt, ‘‘Effective Partition-Driven Placement with Simultaneous Level Processing and Global Net Views,’’ in Proc. of International Conference on Computer-Aided Design, pp. 254-259, 2000.
[88] H. Etawil, S. Areibi, and A. Vannelli, ‘‘Attractor-Repeller Approach for Global Placement,’’ in Proc. of International Conference on Computer-Aided Design, pp. 20-24, 1999.
[89] T. F. Chan, J. Cong, T. Kong, and J. R. Shinnerl, ‘‘Multilevel Optimization for Large-Scale Circuit Placement,’’ in Proc. of International Conference on Computer-Aided Design, pp. 171-176, 2000.
[90] P. H. Madden, ‘‘Reporting of Standard Cell Placement Results,’’ in Proc. of International Symposium on Physical Design, pp. 30-35, 2001.
[91] Y. Jiang and S. S. Sapatnekar, ‘‘An Integrated Algorithm for Combined Placement and Libraryless Technology Mapping,’’ in Proc. of International Conference on Computer-Aided Design, pp. 102-106, 1999.
[92] W. Chen, C. T. Hsieh, and M. Pedram, ‘‘Simultaneous Gate Sizing and Placement,’’ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 206-214, February 2000.
[93] Y. C. Chou and Y. L. Lin, ‘‘A performance-driven standard-cell placer based on a modified force-directed algorithm,’’ in Proc. of International Symposium on Physical Design, pp. 24-29, 2001.
[94] Cadence Design Systems, Inc., ‘‘LEF/DEF Language Reference,’’ Product Version 5.0, February 1997.
[95] http://www.tsmc.com.tw/Technology
[96] http://developer.intel.com/design/tech.htm
[97] Artisan Components Inc., http://artisan.com.