隨著互補式金屬氧化物半導體製程技術進入深次微米時代，製程變異以及生產過程缺陷會使得產品的良率降低，並且常常使得晶片的時序行為出現錯誤。這時對於錯誤的晶片來說，必須要對其做更進一步的分析。然而，即使我們已經依照晶片受到的影響做分類，這個方法仍然有沒考慮到的地方而需要更進一步分析。
在這篇論文中，我們提出了一套方法，收集受到相同製程變異影響的晶片，並且測試錯誤的晶片上所挑選出某一部分的路徑做詳細的時間分析，以這些路徑的時間資訊建立出回歸模型。這個模型能依照電路上的特徵預測受到變異影響的額外延遲，在考慮這些延遲的情況下再次做時間分析。然而在建立回歸模型的過程中，可能會因為一些外來因素，例如隨機性製程變異，或者訓練模型用的資料準備不齊全的關係，使得模型預測的結果並不如預期而造成誤差，因此我們也額外提供一套方法，用已知的時間資訊當作標準，來修復模型可能出現的錯誤，進而提升模型的準確度。
藉此我們可以藉由著測量整個電路一部分的路徑，進而預測出整個電路每條路徑出現錯誤的可能，再針對這些路徑做更深入的測試。如此一來可以有效的提升測試的品質，或者能將這些延遲資訊回饋給下一階段的設計者做出更好的設計。

As the CMOS technology coming to nanometer scale, process variation play an important role
in yield of production. It and defects can reduce a product’s parametric yield. Yet, even we have
categorized chips with above influences, there is a lack of methods to further analyze these effects.
In this paper, we propose to build a regression model from failed chips under the influence of
systematic variations. The inputs of the model are the delay measurements of failed paths. And the
proposed model will use circuit features to generate delay deviations, which can in turn be injected
back to circuits for timing analysis considering variations. Thus, we can predict the probability of
other possibly failing paths in order to select candidates for further test generation. Therefore, test
quality is improved for next batch of chips or better confidence level is achieved for next design
cycle.

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