隨者電晶體微型化進入奈米尺寸的世代，電連結系統將面臨低擴充性、頻寬上的限制、電阻與電容產生之延遲效應…等問題。光晶片連結提供一個好的方案以解決上述之窘境，讓下個世代之多核心之晶片傳輸有更優越之效能表現。
本論文研究在短距離的傳輸系統下所做的光連結系統設計。首先我們設計出高擴充性、低傳輸損耗及低功率耗損之3x3及4x4非阻塞式光切換器，做結構上之分析及訊號傳輸品質評估，並與相關文獻做比較。基於此兩類結構，應用於不同拓樸如環狀及網狀網路，以達多核心晶片間傳輸。最後希望上述之設計方針與分析，能供未來系統設計者做一個參考依據。

As the transistors enters the scales of the nanometer regime, metallic interconnect will be highly inefficient in several issues, such as poor scalability, limited bandwidth, RC delay, and so on. On-chip interconnect implemented in the optical domain has been considered as a promising candidate toward next generation chip multiprocessor (CMP) with advanced performance.
In this study, we mainly focused on designing the communication system in short distance regime. First, we designed 3x3 and 4x4 non-blocking optical switches with high scalability, low propagation loss, and low power consumption. We analyzed the structure, signal quality, and compared with recent literatures. On basis of two frameworks, we applied them to different topologies such as ring and mesh for optical network on chip (ONoC) to achieve chip multiprocessor. Finally, we hope that the design strategies for optical switches and corresponded ONoC will provide a guideline for system level designer for choosing optimized topology in ONoC depending on implementation infrastructure.

[1] 英特爾（Intel）公司網站，http://www.intel.com/
[2] G. Tosik, Z. Lisik, and F. Gaffiot, “Optical interconnections in future VLSI systems,” Telecommunications and information technology 6, 105-108 (2007)
[3] D. A. B. Miller, “Optical interconnects to electronic chips,” Applied Optics 49, F59-F70 (2010)
[4] I. O'Connor, “Optical solutions for system-level interconnect,” International workshop on System level interconnect prediction (SLIP '04) ACM, New York, USA, 79-88 (2004)
[5] G. Grasso, P. Galli, M. Romagnoli, E. Iannone, and A. Bogoni, “Role of Integrated Photonics Technologies in the Realization of Terabit Nodes,” Optical Communications and Networking 1, B111-B119 (2009)
[6] I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” Solid-State Circuits Conference - Digest of Technical Papers, 468-469,469a (2009)
[7] M. Paniccia, “Integrating silicon photonics,” Nature Photonics 4, 498-499 (2010)
[8] M. Hochberg and T. Baehr-Jones, “Towards fabless silicon photonics,” Nature Photonics 4, 492-494 (2010)
[9] K. Bergman, “Silicon Photonic On-Chip Optical Interconnection Networks,” The 20th Annual Meeting of the IEEE - Lasers and Electro-Optics Society, 470-471 (2007)
[10] F. E. Doany, C. L. Schow, C. Baks, R. Budd, Y. Chang, P. Pepeljugoski, L. Schares, D. Kuchta, R. John, J. A. Kash, and F. Libsch, “160-Gb/s Bidirectional Parallel Optical Transceiver Module for Board-Level Interconnects Using a Single-Chip CMOS IC,” Electronic Components and Technology Conference, 1256-1261 (2007)
[11] H. S. Cho, K. Chu, S. Kang, S. H. Hwang, B. S. Rho, W. H. Kim, J. Kim, J. Kim, and H. Park, “Compact packaging of optical and electronic components for on-board optical interconnects,” IEEE Transactions on Advanced Packaging 28, 114-120 (2005)
[12] G. Chen, H. Chen, M. Haurylau, N. Nelson, P. M. Fauchet, E. G. Friedman, and D. Albonesi, “Predictions of CMOS compatible on-chip optical interconnect,” International workshop on System level interconnect prediction (SLIP '05) ACM, New York, USA, 13-20 (2005)
[13] C. Gunn, A. Narasimha, B. Analui, Yi Liang, and T. J. Sleboda, “A 40Gbps CMOS Photonics Transceiver,” Proceedings of SPIE 6477, 64770N.1-64770N.8 (2007)
[14] J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proceedings of SPIE 6125, 61250H.1- 61250H.15 (2006)
[15] A. Scandurra, “Silicon Photonics: The System on Chip Perspective,” Applied Physics 119, 143-168 (2011)
[16] IBM公司網站，http://www.ibm.com/
[17] J. A. Kash, “Leveraging Optical Interconnects in Future Supercomputers and Servers,” 16th IEEE Symposium on High Performance Interconnects, 190-194 (2008)
[18] S. J. Ben Yoo, V. Akella1, R. Amirtharajah, B. Baas, K. Bergman, S. Fan, M. Lipson, D. A. B. Miller, and J. Shalf, “Balanced computing with nanophotonic interconnects,” 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society, 368-369 (2008)
[19] S. J. B. Yoo, “Future prospects of silicon photonics in next generation communication and computing systems,” Electronics Letters 45, 584-588 (2009)
[20] D. A. B. Miller, “Device Requirements for Optical Interconnects to Silicon Chips,” Proceedings of the IEEE 97, 1166-1185 (2009)
[21] D. Liang and J. E. Bowers, “Recent progress in lasers on silicon,” Nature Photonics 4, 511-517 (2010)
[22] J. V. Campenhout, L. Liu, P. R. Romeo, D. V. Thourhout, C. Seassal, P. Regreny, L. D. Cioccio, J. Fedeli, and R. Baets, “A Compact SOI-Integrated Multiwavelength Laser Source Based on Cascaded InP Microdisks,” IEEE Photonics Technology Letters 20, 1345-1347 (2008)
[23] http://www.research.ibm.com/photonics/publications/ecoc_tutorial_2008.pdf
[24] A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “Electrically pumped hybrid AlGaInAs-silicon evanescent laser,” Optics Express 14, 9203-9210 (2006)
[25] L. Liu, G. Roelkens, J. V. Campenhout, J. Brouckaert, D. V. Thourhout, and R. Baets, “III–V/Silicon-on-Insulator Nanophotonic Cavities for Optical Network-on-Chip,” Nanoscience and Nanotechnology 10, 1461-1472 (2010)
[26] Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435, 325-327 (2005)
[27] A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia, “A high-speed silicon optical modulator based on a metal–oxide–semiconductor capacitor,” Nature 427, 615-618 (2004)
[28] G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nature Photonics 4, 518-526 (2010)
[29] Helios project，http://www.helios-project.eu/
[30] 張忠興，轉角中空光波導的研製，國立中央大學光電科學與工程學研究所碩士學位論文，2009。
[31] M. Lipson, “Guiding, modulating, and emitting light on Silicon-challenges and opportunities,” Lightwave Technology 23, 4222- 4238 (2005)
[32] B. G. Lee, X. Chen, A. Biberman, X. Liu, I. Hsieh, C. Chou, J. I. Dadap, F. Xia, W. M. J. Green, L. Sekaric, Y. A. Vlasov, and K. Bergman, “Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks,” IEEE Photonics Technology Letters 20, 398-400 (2008)
[33] K. K. Lee, D. R. Lim, L. C. Kimerling, J. Shin, and F. Cerrina, “Fabrication of ultralow-loss Si/SiO2 waveguides by roughness reduction,” Optics Letters 26, 1888-1890 (2001)
[34] 趙師章，利用雙光子聚合技術製作高耦合效率波導陣列光纖耦合器，國立中央大學光電科學與工程學研究所碩士學位論文，2010。
[35] A. A. Aboketaf, A. W. Elshaari, and S. F. Preble, “Optical time division multiplexer on silicon chip,” Optics Express 18, 13529-13535 (2010)
[36] C. R. Pollock and M. Lipson, “Integrated Photonics,” Kluwer Academic Publishers, (2003)
[37] G. Cocorullo, F. G. Della Corte, I. Rendina, and P. M. Sarro, “Thermo-optic effect exploitation in silicon microstructures,” Sensors and Actuators A: Physical 71, 19-26 (1998)
[38] W. M. J. Green, H. F. Hamann, L. Sekaric, M. J. Rooks, and Y. A. Vlasov, “Ultra-compact reconfigurable silicon optical devices using micron-scale localized thermal heating,” Optical Fiber Communication and the National Fiber Optic Engineers Conference, 1-3 (2007)
[39] N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4x4 hitless Silicon router for optical Networks-on-Chip,” Optics Express 16, 19395-19395 (2008)
[40] A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection,” Proceedings of the IEEE 97, 1216-1238 (2009)
[41] A. Kaz´mierczak, W. Bogaerts, E. Drouard, F. Dortu, P. Rojo-Romeo, F. Gaffiot, D. V. Thourhout, and D. Giannone, “Highly Integrated Optical 4x4 Crossbar in Silicon-on-Insulator Technology,” Lightwave Technology 27, 3317-3323 (2009)
[42] J. Chan, G. Hendry, A. Biberman, and K. Bergman, “Architectural Exploration of Chip-Scale Photonic Interconnection Network Designs Using Physical-Layer Analysis,” Lightwave Technology 28, 1305-1315 (2010)
[43] Y. Xie, M. Nikdast, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk Noise and Bit Error Rate Analysis for Optical Network-on-Chip,” The 47th Design Automation Conference, (2010)
[44] B. E. Little, S. T. Chu, H. A. Haus, J. Foresi, and J.-P. Laine, “Microring resonator channel dropping filters,” Lightwave Technology 15, 998-1005 (1997)
[45] H. L. R. Lira, S. Manipatruni, and M. Lipson, “Broadband hitless silicon electro-optic switch 
for on-chip optical networks,” Optics Express 17, 22271-22280 (2009)
[46] B. E. A. Saleh and M. C. Teich, “Fundamentals of Photonics, 2nd Edition,” John Wiley and Sons Incorporation, (2007)
[47] A. Biberman, H. L. R. Lira, K. Padmaraju, N. Ophir, J. Chan, M. Lipson, and K. Bergman, “Broadband Silicon Photonic Electrooptic Switch for Photonic Interconnection Networks,” IEEE Photonics Technology Letters 23, 504-506 (2011)
[48] Y. Vlasov, W. M. J. Green, and Fengnian Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nature Potonics 2, 242-246 (2008)
[49] F. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nature Potonics 1, 65-71 (2007)
[50] http://mnp.ucsd.edu/ece240a_2009/chapter_microring.pdf
[51] S. Xiao, M. H. Khan, H. Shen, and M. Qi, “Multiple-channel silicon micro-resonator based filters for WDM applications,” Optics Express 15, 7489-7498 (2007)
[52] J. Van Campenhout, W. M. Green, S. Assefa, and Y. A. Vlasov, “Low-power, 2×2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks,” Optics Express 17, 24020-24029 (2009)
[53] D. V. Thourhout, I. O'Connor, A. Scandurra, L. Liu, W. Bogaerts, S. Selvaraja, and G. Roelkens, “Nanophotonic Devices for Optical Networks-on-Chip,” Lasers and Electro-Optics/International Quantum Electronics, (2009)
[54] G. Singh, R. P. Yadav, and V. Janyani, “Integrated MMI couplers based 4×4 all optical switch with absolute loss uniformity,” Photonics Letters of Poland 1, 187-189 (2009)
[55] H. Liu, H. Tam, P. K. A. Wai, and E. Pun, “Low-loss waveguide crossing using a multimode interference structure,” Optics Communications 241, 99-104 (2004)
[56] P. Sanchis, P. Villalba, F. Cuesta, A. Håkansson, A. Griol, J. V. Galán, A. Brimont, and J. Martí, “Highly efficient crossing structure for silicon-on-insulator waveguides,” Optics Letters 34, 2760-2762 (2009)
[57] 高騏勳，具光柵結構之新型雙模干涉分波多工器，國立成功大學微電子工程研究所碩士學位論文，2004。
[58] A. K. Kodi and A. Louri, “RAPID: Reconfigurable and Scalable All-Photonic Interconnect for Distributed Shared Memory Multiprocessors,” Lightwave Technology 22, 2101-2110 (2004)
[59] A. K. Kodi and A. Louri, “RAPID for high-performance computing systems: architecture and performance evaluation,” Applied Optics 45, 6326-6334 (2006)
[60] A. K. Kodi and A. Louri, “System simulation methodology of optical interconnects for high-performance computing systems,” Optical Networking 6, 1282-1300 (2007)
[61] S. Umarani, S. Pavai Madheswari, and N. Nagarajan, “Literature Survey of nonblocking network topologies,” The 12th international conference on Networking, 336-341 (2010)
[62] A. Shacham, K. Bergman, and L. P. Carloni, “On the Design of a Photonic Network-on-Chip,” First International Symposium on Networks-on-Chip, 53-64 (2007)
[63] A. Shacham, K. Bergman, and L. P. Carloni, “Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors,” IEEE Transactions on Computers 57, 1246-1260 (2008)
[64] M. Petracca, B. G. Lee, K. Bergman, and L. P. Carloni, “Photonic NoCs: System-Level Design Exploration,” Micro, IEEE 29 74-85 (2009)
[65] A. Shacham, B. G. Lee, A. Biberman, K. Bergman, and L. P. Carloni, “Photonic NoC for DMA Communications in Chip Multiprocessors,” 15th Annual IEEE Symposium on High-Performance Interconnects, 29-38 (2007)
[66] F. N. Sibai, “Which On-Chip Interconnection Network for 16-core MPSoCs?,” International Conference on Complex, Intelligent and Software Intensive Systems, 625-630 (2010)
[67] A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of Optical Interconnects Based on Microring Resonators,” IEEE Photonics Technology Letters 22, 1081-1083 (2010)
[68] A. Bianco, D. Cuda, M. Garrich, R. Gaudino, G. Gavilanes, P. Giaccone, and F. Neri, “Optical Interconnection Networks Based on Microring Resonators,” IEEE International Conference on Communications,1-5 (2010)
[69] M. Garrich, “Optical Interconnections based on Microring Resonators,” POLITECNICO DI TORINO (2009)
[70] L. Zhang, M. Yang, Y. Jiang, and E. Regentova, “Architectures and routing schemes for optical network-on-chips,” Computers and Electrical Engineering 35, 856-877 (2008)
[71] A. Biberman, G. Hendry, J. Chan, H. Wang, K. Bergman, K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “CMOS-compatible scalable photonic switch architecture using 3D-integrated deposited silicon materials for high-performance data center networks,” Optical Fiber Communication Conference and Exposition,1-3 (2011)
[72] X. Yin, H. Gu, H. Ju, and L. Jia, “An Electro Optical Honeycomb Networks-on-Chip based on a New Nonblocking Switch,” The 23rd International Technical Conference on Circuits/Systems, 1801-1804 (2008)
[73] G. I. Papadimitriou, C. Papazoglou, and A. S. Pomportsis, “Optical switching: switch fabrics, techniques, and architectures,” Lightwave Technology 21, 384- 405 (2003)
[74] B. G. Lee, A. Biberman, D. Po, M. Lipson, and K. Bergman, “All-Optical Comb Switch for Multiwavelength Message Routing in Silicon Photonic Networks,” IEEE Photonics Technology Letters 20, 767-769 (2008)
[75] W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides,” Optics Letters 32, 2801-2803 (2007)
[76] M. Yang, W. M. J. Green, S. Assefa, J. V. Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-Blocking 4x4 Electro-Optic Silicon Switch for On-Chip Photonic Networks,” Optics Express 19, 47-54 (2011)
[77] J. Chan, A. Biberman, B. G. Lee, and K. Bergman, “Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications,” 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society, 300-301 (2008)
[78] A. Parini, L. Ramini, G. Bellanca, and D. Bertozzi, “Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness,” The Fifth International Workshop on Interconnection Network, 31-34, (2011)
[79] A. W. Poon, F. Xu, and X. Luo, “Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip,” Proceedings of SPIE 6898, 689812.1-689812.10 (2008)
[80] Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Optics Express 15, 430-436 (2007)
[81] H. Gu, K. H. Mo, J. Xu, and W. Zhang, “A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip,” IEEE Computer Society Annual Symposium on VLSI, 19-24 (2009)
[82] K. Sato, L. Wosinska, J. Wu, and Y. Ji, “Performance evaluation for optical network-on-chip interconnect architectures,” Proceedings of the SPIE 7633, 76330S.1-76330S.8 (2009)
[83] Z. Chang and J. Tang, Y. Jin, “An insertion loss balance aware routing scheme in photonic network on chip,” 7th International Conference on Information - Communications and Signal Processing, 1-5 (2009)
[84] R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Optics Express 19, 18945-18955 (2011)
[85] J. Chan, G. Hendry, K. Bergman, and L. P. Carloni, “Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, 1507-1520 (2011)
[86] J. Cardenas, C. B. Poitras, J. T. Robinson, K. Preston, L. Chen, and M. Lipson, “Low loss etchless silicon photonic waveguides,” Optics Express 17, 4752-4757 (2009)