高介電材料於高遷移率砷化銦鎵：達到低界面陷阱態密度及高性能自動對準反轉式通道MOSFET之研發

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研究生：	邱漢欽 Chiu, Han-Chin
論文名稱：	高介電材料於高遷移率砷化銦鎵：達到低界面陷阱態密度及高性能自動對準反轉式通道MOSFET之研發 High-κ dielectrics on high carrier mobility InGaAs: achieving low interfacial density of states and high-performance self-aligned inversion-channel MOSFETs
指導教授：	洪銘輝 Hong, Minghwei 郭瑞年 Kwo, Raynien
口試委員:	鄭克勇 Cheng, K. Y. 劉致為 Liu, C. W. 郭治群 Guo, J. C. 皮敦文 Pi, P. W. 王永和 Wang, Y. H. 賴聰賢 Lay, T. S.
學位類別：	博士 Doctor
系所名稱：	工學院 - 材料科學工程學系 Materials Science and Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	116
中文關鍵詞：	砷化鎵、砷化銦鎵、高速電子、原子層沉層、高介電、界面陷阱態密度、三五金氧半電晶體、三五族半導體製程、自動對準
外文關鍵詞：	GaAs, InGaAs, high mobility, atomic-layer-deposition (ALD), high-k, interfacial density of states, III-V MOSFET, Conductance method, Quasi-state CV, Fermi-level movement efficiency, III-V process, Self-aligned, ICP-RIE
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Atomic-layer-deposited Al2O3 on In0.53Ga0.47As with short air-exposure between the oxide and semiconductor deposition without any InGaAs surface treatments has shown negligible frequency-dispersion capacitance-voltage (CV) characteristics in the depletion and accumulation region, and well-behaved frequency-dependent inversion curves. The interfacial density of states (Dit) of the metal-oxide-semiconductor capacitor (MOSCAP) was determined by the Terman method and the conductance method. The Dit distribute over the bandgap of In0.53Ga047As in “U”-shape giving lower Dit values near the mid-gap were obtained about 5×1011-3×1012 eV-1cm-2. By the conductance method, however, the Dit values were adopted as the authentic values and the Dit close to the mid-gap is about 3×1012 eV-1cm-2. The quasi-static CV characteristics indicate a high efficiency of 63% for the Fermi-level movement efficiency near the mid-gap.
On the basis of the high quality Al2O3/InGaAs interface, self-aligned enhancement-mode (E-mode) inversion-channel InxGa1-xAs (x=0.53 and 0.75) n-MOSFETs using atomic-layer-deposited Al2O3 as the gate dielectric have been demonstrated. Devices with lower dopant activation temperature (DAT) and higher indium content channel show better output DC characteristics. A low subthreshold swing ~ 103 mV/dec was obtained from the In0.75Ga0.25As MOSFETs with DAT of 600oC; furthermore, a maximum drain current (IDS) ~ 1.1 mA/μm was measured at a drain-to-source voltage of 1 V from a 350-nm gate-length device, the highest value among all enhancement-mode inversion-channel n-MOSFETs using InGaAs as the channels and ex-situ grown high-□ dielectrics. In addition, device optimization including TiN gate metal etching by ICP-RIE, channel doping, S/D implantation, and channel engineering were also studied in this work.

Table of Contents
Publication List………………………………...……………………….I
Abstract………………………………………...………………………III
Table of Contents……………………………………………………...V
List of Figures………………………………………………………VIII
List of Tables…………………………………………………….…XIV
Chapter 1 Introduction………………………………………………..1
1.1 Background and Motivation…...……………………………………………1
1.2 Alternative channel materials…………………………………………………2
1.3 High-κ Dielectric on InGaAs……...….…………………….......................….5
1.4 High-κ/InGaAs Interface Characterization……………………………...……7
1.5 Device Structure……………………...………………………....…………….9
Chapter 2 Instrumentation and Theories……...……………………..19
2.1 Atomic Layer Deposition (ALD)……...……….…………………….…...19
2.2 Heat Treatment………………………...………...………………………....20
2.3 Inductively Coupled Plasma Reactive Ion Etching……....…….……......21
2.4 Electrical Measurement Instruments…..…………………..………....……23
2.4.1 Agilent 4284A Precision LCR Meter………...…………………….23
2.4.2 Agilent 4156C Semiconductor Parameter Analyzer....……..……...23
2.5 Basic Principle of Metal-Oxide-Semiconductor Capacitor.......................27
2.5.1 Capacitance-Voltage characteristics of a MOSCAP........................27
2.5.2 Determination of Oxide Dielectric Constant, Doping Concentration
, and Flat-Band Voltage  from a Capacitance-Voltage Curve…….…30
2.5.3 Extraction of Interfacial Density of States………….…………….32
2.5.3.1 Terman Method…….………………………………………..34
2.5.3.2 Conductance Method………………………………………..35
2.6 Transfer Length Method…………………………………………………38
Chapter 3 Achieving a Low Interfacial Density of States in Atomic Layer Deposited Al2O3 on In0.53Ga0.47As and Electrical Characterization……...………………………..…………..41
3.1 Introduction…………………………………………………….…………41
3.2 Sample Preparation……………………………………………………….42
3.3 ALD-Al2O3 Film Optimization by Heat Treatment………………........43
3.4 Process for Fabricating Al2O3/InGaAs MOS Capacitors………….......46
3.5 Electrical Characteristics…………………………………………………49
3.5.1 Low Leakage Current of 10-nm thick Atomic-Layer- Deposited
Al2O3 Film………………………………………………………….49
3.5.2 Capacitance-Voltage Characteristics………………………………50
3.5.3 Interfacial Density of States Extraction………………………….52
3.5.3.1 Terman Method……………………………………………..52
3.5.3.2 Conductance Method……………………………………....54
3.5.3.3 Quasi-Static Capacitance-Voltage Measurement and Fermi-
Level Movement Efficiency………………………………..56
3.5.3.4 Charge Pumping Method……...…………………………..61
3.5.3.5 Summary……………...………....…………………………..66
Chapter 4 Self-aligned Inversion-Channel InxGa1-xAs (x=0.53 and 0.75) MOSFETs using ALD-Al2O3 as Gate Dielectrics...70
4.1 Introduction…………………………………………………….…………70
4.2 Sample Preparation……………………………………………………….71
4.3 Self-aligned Process for Fabricating MOSFETs..……………………...71
4.3.1 Formation of Self-algined Gate – Titanium Nitride Etched by
ICP-RIE…………………………………………………………..71
4.3.2 Self-aligned Process for Fabricating MOSFETs………………73
4.4 Device Characteristics of InGaAs MOSFETs……………………….…82
4.4.1 DC and RF Characteristics In0.53Ga0.47As N-MOSFET with 10-
nm Thick ALD-Al2O3 as a Gate Dielectric……………………….82
4.4.2 Electrical Characteristics In0.53Ga0.47As N-MOSFET with 5-nm
Thick ALD-Al2O3 as a Gate Dielectric and 0.6 μm Gate Length...89
4.4.3 High Performance Self-aligned inversion-channel In0.75Ga0.25As
 N-MOSFET with 5-nm Thick ALD-Al2O3 as a Gate Dielectric…96
4.4.4 Comparison……………………………………………………...101
4.4.5 Submicron-meter gate length ALD-Al2O3/In0.75Ga0.25As
MOSFETs…………….…………………………………………103
4.5 Benchmark………………………………………………………………109
Chapter 5 Conclusion……………………………………………….115
 
List of Figures
Fig. 1-1 Scaling of actual transistor size with technology node to comply with Moore’s Law. Nodes with feature size less than 100 nm can be referred to as nanotechnology. ………………………………………………………………………1
Fig. 1-2 Normalized energy-delay product of n channel InSb and InGaAs quantum well transistors compared with that of standard silicon metal oxide semiconductor field-effect transistors. ………………………………………………………………3
Fig. 1-3 Schematic illustration of an inversion-channel (surface channel) MOSFET. .6
Fig. 1-4 Simple structure of a MOS capacitor to be commonly used to measure the electrical characteristics. ……………………………………………………………...8
Fig. 1-5 Cross-sectional view of (a) a conventional MOSFET, (b) a HEMT, and (c) a buried channel MOSFET. …………………………………………………………11
Fig. 1-6 Band diagrams corresponding to device structures of Fig. 1-5. Ec, Ev, Ei, and Ef represent conduction band, valence band, intrinsic Fermi-level, and Fermi-level of semiconductor, respectively. ……………………………………………………….12
Fig. 2-1 Schematic illustration of one-cycle ALD process. …………………………20
Fig. 2-2 Schematic illustration of ICP-RIE. …………………………………………21
Fig. 2-3 ICP-RIE system – ULVAC CE-300I. ………………………………………22
Fig. 2-4 Rectangular approximation method used by the Agilent 4156C. Note that the Area is equal to charge Q. …………………………………………………………25
Fig. 2-5 QSCV measurement sequrence. …………………………………………….26
Fig. 2-6 Ideal band bendings of a MOSCAP under a gate bias. ……………………27
Fig. 2-7 Ideal equivalent circuit for a MOSCAP at low frequency. …………………29
Fig. 2-8 Ideal CV curve of a MOSCAP. ……………………………………………..30
Fig. 2-9 Equivalent circuit for a MOSCAP with interfacial traps at low frequency. ..33
Fig. 2-10 High-frequency CV curves with and without Dit contributions, respectively…………………………………………………………………………...34
Fig. 2-11 Equivalent circuits for conductance measurement; (a) original circuit of a MOSCAP with Rit in series with Cit, (b) simplify (a) as Cp and Gp in parallel, (c) simplify (b) as Cm and Gm in parallel. ………………………………………………36
Fig. 2-12 Basic plot of Gp/ω versus ω. ………………………………………………37
Fig. 2-13 A transfer length method test pattern. ……………………………………..38
Fig. 2-14 A typical plot of total resistance (RT) versus spacing (d). ………………39
Fig. 3-1 The hysteresis CV curves of (a) as-deposited, (b) 375oC F.G. annealing, and (c) 300oC N2 annealing at 10 kHz. …………………………………………………44
Fig. 3-2 (a) Layout - 1st – Gate dots /Alignment marks (b) cross-sectional schematic view of structure after 1st mask lithography. ………………………………………47
Fig. 3-3 (a) Layout – 2nd – Ohmic metal (b) cross-sectional schematic view of structure after 2nd mask lithography. ………………………………………………48
Fig. 3-4 Gate leakage current density (J) as a function of gate electrical field (E). …50
Fig. 3-5 CV characteristics of the MOSCAP - TiN/Al2O3 (10 nm)/n-In0.53Ga0.47As  at various ac frequencies from 1k to 1M Hz. …………………………………………51
Fig. 3-6 Hysteresis curve of the MOSCAP - TiN/Al2O3 (10 nm)/n-In0.53Ga0.47As at 1 MHz. …………………………………………………………………………………51
Fig. 3-7 (a) Ideal CV vs. measured CV curves. (b) Dit (with error bars) distribution within bandgap for the TiN/Al2O3 (10 nm)/n-In0.53Ga0.47As MOSCAP. Ec and Ev represent conduction band and valence band, respectively. …………………………53
Fig. 3-8 (a) Gp/ω versus frequency (f). (b) Distribution of Dit versus energy. Note that Ef and Ec are the Fermi-level and conduction band, respectively. …………………..55
Fig. 3-9 QSCV measured with various sweep rates (50 to 1 mV/s) from inversion to accumulation. ………………………………………………………………………57
Fig. 3-10 ψs-VG relationship extracted from QSCV curve with a sweep rate of 1mV/sec. ……………………………………………………………………………..58
Fig. 3-11 FLME extraction from the ψs-VG relationship. ……………………………59
Fig. 3-12 Differential FLME of Fig.3-11. …………………………………………...60
Fig. 3-13 (a) top and (b) cross-sectional schematic view of a structure designed for the charge-pumping measurement……………………………………………………..62
Fig. 3-14 Charge pumping current (Icp) as function of gate pulse with frequency dependence. The inset shows Gp/ω versus frequency under different voltages measured by the conductance method………………………………………………64
Fig. 3-15 Profile of the volume densities of bulk traps (Nbt) in ALD-Al2O3 as a function of distance from the In0.53Ga0.47As surface…………………………………65
Fig. 3-16 Dit distribution vs energy for ALD-Al2O3/In0.53Ga0.47As derived by Terman method (red), conductance method (blue), and charge pumping method (green), respectively…………………………………………………………………………66
Fig. 4-1 Layout-1st Alignment mark + self-aligned gate of unit cell and one device..76
Fig. 4-2 Layout – 2nd Self-algined implantation of unit cell and one device. ……….77
Fig. 4-3 Layout – 3rd Source/drain contacts of unit cell and one device. ……………78
Fig. 4-4 Layout – 4th P-well Contacts of unit cell and one device. ………………….79
Fig. 4-5 Layout – 5th Pad contacts of unit cell and one device. ……………………..80
Fig. 4-6 Layout of the design for various electrical measurements. ………………81
Fig. 4-7 SEM image of a single device. ……………………………………………..81
Fig. 4-8 Device structure for a MOSFET with 10-nm thick ALD-Al2O3. ……..……82
Fig. 4-9 (a) DC IDS-VDS characteristics of a 100μm×1μm(W×Lmask) self-aligned inversion-channel ALD-Al2O3/In0.53Ga0.47As n-MOSFET. (b) log(IDS) and Gm as function of gate bias. ………………………………………………………………...84
Fig. 4-10 Linear extrapolation of IDS versus VGS curve at VDS=0.1V. ………………85
Fig. 4-11 Gate length of mask (Lmask) versus total measured resistance (Rtotal) at VGS=4V………………………………………………………………………………85
Fig. 4-12 Gate-to-source and gate-to-body leakage currents versus gate bias (Vg) of the device shown in Fig. 4-9. ………………………………………………………..86
Fig. 4-13 Plot of effective electron mobility (μeff) as a function of inversion charge density (Ninv). ………………………………………………………………………87
Fig. 4-14 (a) RF performance of a 50μm×1μm(W×Lmask) ALD-Al2O3/In0.53Ga0.47As inversion-channel n-MOSFET at VDS=2V and VGS=1.5V. (b) Frequency response as a function of gate bias at VDS =2V. ……………………………………………………88
Fig. 4-15 Device structure for an In0.53Ga0.47AsMOSFET with 5-nm thick ALD-Al2O3. ………………………………………………………………………….90
Fig. 4-16 (a) DC IDS-VDS characteristics of a 100μm×0.6μm self-aligned inversion-channel ALD-Al2O3(5nm)/In0.53Ga0.47As n-MOSFET. (b) log(IDS) and Gm as function of gate bias at VDS =4V and 0.1V, respectively. ………………………...91
Fig. 4-17 Scaling characteristics of IDS and maximum Gm versus inverse of gate lengths for inversion-channel 5nm-Al2O3/p-In0.53Ga0.47As MOSFETs. ……………..92
Fig. 4-18 Threshold voltage and subthreshold swing (S.S.) versus gates lengths for inversion-channel 5nm- Al2O3/p-In0.53Ga0.47As MOSFETs. ………………………...92
Fig. 4-19 HR-XPS spectra of O 1s, Al 2p, As 3d, and In 3d core-level of as-deposited,  650oC-RTA, and 750 oC-RTA ALD-Al2O3/In0.53Ga0.47As. ………………………....95
Fig. 4-20 HR-XPS spectra of O 2s and Ga 2p3/2 core-level spectra of as-deposited, 650oC-RTA, and 750oC-RTA ALD- Al2O3/In0.53Ga0.47As. …………………………96
Fig. 4-21 Device structure for an In0.75Ga0.25As MOSFET with 5-nm thick ALD-Al2O3 as a gate dielectric. ……………………………………………………..97
Fig. 4-22 Improvements of transfer characteristics in In0.75Ga0.25As MOSFETs with dopant activation temperatures (DATs) of 600oC and 650oC, respectively. (a) IDS-VDS curves and (b) IDS and Gm as function of gate bias bias at VDS =2V. ………………..99
Fig. 4-23 (a) DC IDS-VDS characteristics of a 50μm×1μm self-aligned inversion-channel ALD-Al2O3(6nm)/In0.75Ga0.25As n-MOSFET. (b) IDS and Gm as function of gate bias at VDS =2.5V. ………………………………………………100
Fig. 4-24 Drain current and peak transconductance versus inverse of gate-length (1/Lg) for ALD-Al2O3/p-In0.75Ga¬0.25As MOSFETs. ……………………………………….101
Fig. 4-25 (a) IDS-VGS and (b) Gm-VGS characteristics of the ALD-Al2O3(5nm)/ (In0.75Ga0.25As/)In0.53Ga0.47As nMOSFETs (LG = 8 μm) with various S/D dopant activation temperature (DAT) at VDS=50mV. ……………………………………102
Fig. 4-26 (a) IDS versus VDS as a function of VGS for ALD-Al2O3(5nm)/ In0.75Ga0.25As(5nm)/In0.53Ga0.47As n-MOSFETs with LG of 350 nm. (b) extrinsic and intrinsic transconductances (Gm) versus VGS at VDS=1V. ………………………….104
Fig. 4-27 (a) IDS versus VDS as a function of VGS for ALD-Al2O3(5nm)/ In0.75Ga0.25As(5nm)/In0.53Ga0.47As n-MOSFETs with LG of 200 nm. (b) IDS versus VGS at VDS=1.5V. ………………………………………………………………..………105
Fig. 4-28 Process flow of fabricating self-aligned inversion-channel ALD-Al2O¬3 In0.75Ga0.25As/In0.53Ga0.47As MOSFETs with LDD structure. ……………………...106
Fig. 4-29 (a) IDS versus VGS of a 500nm inversion-channel ALD-Al2O3/In0.75Ga0.25As MOSFET measured at drain voltages of 0.5 V and 1.5 V, respectively, showing a DIBL of 39mV/V. (b) IDS versus VGS between MOSFETs with and without LDD structure. ……………………………………………………………………………108

Fig. 4-30 Summary of (a) maximum IDS and (b) peak Gm of representative work on InxGa1-xAs (x≧0.53) E-mode inversion-channel nMOSFETs with ALD or MOCVD oxide as gate dielectric. Devices with gate-length shorter than 1μm are included. The number near each data point indicates the In content (x) of the InxGa1-xAs channel used in corresponding device. ……………………………………………………...111











List of Tables
Table 1-I. Physical properties of commonly used semiconductors. ………………..…4
Table 1-II. Comprehensive comparisons of different device structures. ……………14
Table 3-I. Parameters used for QSCV measurement by Agilent 4156C. …………....57
Table 4-I. Boiling points and formation enthalpies of titanium halides. ……………72
Table 4-II. Etching recipe for etching TiN by ICP-RIE. …………………………….73
Table 4-III. Self-aligned Process Flow (I) (II). …………………………..………74/75
Table 4-IV. Summary of devices with different oxide thicknesses, channel doping concentrations, implanted doses, and dopant-activation temperatures. ……………..94

                                

(Chapter 1)
[1] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications”, IEEE Trans. Nanotechnol., vol. 4, 153 (2005).
[2] S. Datta, G. Dewey, M. Doczy, B. S. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick, R. Chau, “High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stack”, in Int. Electron Devices Meeting Tech. Dig., 2003, 653.
[3] C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand, “45nm High-k + metal gate strain-enhanced transistors”, in VLSI Symp. Tech. Dig., 2008, 128.
[4] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau, “Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout”, in VLSI Symp. Tech. Dig., 2003, 133.
[5] R. Chau, Proceedings of the CS MANTECH Conference, Chicago, IL, 14, April 2008.
[6] NSM Archive website - http://www.ioffe.rssi.ru/SVA/NSM/Semicond/index.html
[7] Y. Q. Wu, W. K. Wang, O. Koybasi, D. N. Zakharov, E. A. Stach, S. Nakahara,J. C. M. Hwang, and P. D. Ye, “0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode In0.75Ga0.25As MOSFET”, IEEE Electron Device Lett., 30, 700 (2009).
[8] U. Singisetti, M. A. Wistey, G. J. Burek, A. K. Baraskar, B. J. Thibeault, A. C. Gossard,M. J. W. Rodwell, B. Shin, E. J. Kim, P. C. McIntyre, B. Yu, Y. Yuan, D. Wang, Y. Taur, P. Asbeck, and Y. J. Lee, “In0.53Ga0.47As Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth”, IEEE Electron Device Lett., 30, 1128 (2009).
[9] Y. T. Chen, H. Zhao, Y. Wang, F. Xue, F. Zhou, and J. C. Lee, “Fluorinated HfO2 gate dielectric engineering on In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors”, Appl. Phys. Lett., 96, 103506 (2010).
[10] H. C. Chin, X. Gong, X. Liu, and Y. C. Yeo, “Lattice-Mismatched In0.4Ga0.6As Source/Drain Stressors With In Situ Doping for Strained In0.53Ga0.47As Channel n-MOSFETs”, IEEE Electron Device Lett., 30, 805 (2009).
[11] D. H. Kim and J. A. del Alamo, “30-nm InAs Pseudomorphic HEMTs on an InP Substrate With a Current-Gain Cutoff Frequency of 628 GH”, IEEE Electron Device Lett., 29, 830 (2008).
[12] T. D. Lin, H. C. Chiu, P. Chang, L. T. Tung, C. P. Chen, M. Hong, J. Kwo, W. Tsai, and Y. C. Wang, “High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-emiconductor field-effect-transistor with Al2O3/ Ga2O3(Gd2O3) as gate dielectrics”, Appl. Phys. Lett., 93, 033516 (2008).
[13] H. C. Lin, W. E. Wang, G. Brammertz, M. Meuris, M. Heyns, “Electrical study of sulfur passivated In0.53Ga0.47As MOS capacitor and transistor with ALD Al2O3 as gate insulator”, Microelectron. Eng., 86, 1554 (2009).
[14] M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu*, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah,and Robert Chau, “Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications”, in Int. Electron Devices Meeting Tech. Dig., 2009, 319.
[15] J. P. de Souza, E. Kiewra, Y. Sun, A. Callegari, D. K. Sadana, G. Shahidi, D. J. Webb, J. Fompeyrine, R. Germann, C. Rossel, and C. Marchiori, “Inversion mode n-channel GaAs field effect transistor with high-k/metal gate,” Appl. Phys. Lett., 92, 153508 (2008).
[16] A. M. Sonnet, C. L. Hinkle, M. N. Jivani, R. A. Chapman, G. P. Pollack, R. M. Wallace, and E. M. Vogel, “Performance enhancement of n-channel inversion type InxGa1-xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer,” Appl. Phys. Lett., 93, 122109 (2008).
[17] H. C. Chin, M. Zhu, C. H. Tung, G. S. Samudra, and Y. C. Yeo, “In-situ Surface Passivation and CMOS-Compatible Palladium-Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs,” IEEE Electron Device Lett., 29, 553 (2008).
[18] E. Yablonovitch, C. J. Sandroff, R. Bhat, and T. Gmitter, “Nearly ideal electronic properties of sulfide coated GaAs surfaces”, Appl. Phys. Lett., 51, 439 (1987).
[19] N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, “InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition”, Appl. Phys. Lett., 89, 163517 (2006).
[20] Y. Xuan, H. C. Lin, and P. D. Ye, “Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High-κ Dielectrics”, IEEE Trans. Electron Devices, 54, 1811 (2007).
[21] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, “Surface passivation of III-V compound semiconductors using atomic-layer-deposition-grown Al2O3”, Appl. Phys. Lett., 87, 252104 (2005).
[22] M. Hong, M. Passlack, J. P. Mannaerts, J. Kwo, S. N. G. Chu, N. Moriya, S. Y. Hou, and V. J. Fratello, “Low interface state density oxide-GaAs structures fabricated by in situ molecular beam epitaxy”, J. Vac. Sci. Technol. B, 14, 2297 (1996).
[23] F. Ren, M. Hong, W. S. Hobson, J. M. Kuo, J. R. Lothian, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, “Demonstration of enhancement-mode p- and n-channel GaAs MOSFETs with Ga2O3(Gd2O3) as gate oxide”, Solid-State Electron., 41, 1751 (1997).
[24] E.H. Nicollian and J.R. Brews, “MOS (Metal Oxide Semiconductor) Physics and Technology”, (Wiley-Interscience, Hoboken, N.J.) 2003.
[25] L. M. Terman, “An investigation of Surface States at a Silicon/Silicon Oxide Interface Employing Metal-Oxide-Silicon Diodes”, Solid-State Electron., 5, 285 (1962).
[26] C. N. Berglund, “Surface States at Steam-Grown Silicon-Silicon Dioxide Interfaces”, IEEE Trans. Electron Devices, 12, 701 (1996).
[27] D. V. Lang, “Deep-level transient spectroscopy: A new method to characterize traps in semiconductors”, J. Appl. Phys., 45, 3023 (1974).
[28] J. S. Brugler and P. G. A. Jespers, “Charge Pumping in MOS Devices”, IEEE Trans. Electron Devices, 16, 297 (1969).
[29] Y. Sun, S. J. Koester, E. W. Kiewra, K. E. Fogel, D. K. Sadana, D. J. Webb, J. Fompeyrine, J. P. Locquet, M. Sousa, and R. Germann, “Buried-channel In0.70Ga0.30As/In0.52Al0.48As MOS capacitors and transistors with HfO2 gate dielectrics”, in Device Research Conference Dig., 2009, 49.
[30] R. J. W. Hill, R. Droopad, D. A. J. Moran, X. Li, H. Zhou, D. Macintyre, S. Thoms, O. Ignatova, A. Asenov, K. Rajagopalan, P. Fejes, I.G. Thayne and M. Passlack, “1 mm gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 mS/mm”, Electron. Lett., 44, 1283 (2008).
[31] Y. Sun, E. W. Kiewra, J. P. de Souza, J. J. Bucchignano, K. E. Fogel, D. K. Sadana, and G. G. Shahidi, “High-Performance In0.7Ga0.3As-Channel MOSFETs With High-κ Gate Dielectrics and α-Si Passivation”, IEEE Electron Device Lett., 30, 5 (2009).
[32] H. C. Chiu, P. Chang, M. L. Huang, T. D. Lin, Y. H. Chang, J. C. Huang, S. Z. Chen, J. Kwo, W. Tsai, and M. Hong, “High performance self-aligned inversion-channel MOSFETs with In0.53Ga0.47As channel and ALD-Al2O3 gate dielectric”, in Device Research Conference Dig., 2009, 83.
[33] T. D. Lin, H. C. Chiu, P. Chang, Y. H. Chang, Y. D. Wu, M. Hong, and J. Kwo, “Self-aligned inversion-channel In0.75Ga0.25As metal-oxide-semiconductor field-effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3 as gate dielectrics”, Solid-State Electron., 54, 919 (2010).
[34] Y. Xuan, Y. Q. Wu, H. C. Lin, T. Shen, and P. D. Ye, “Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric”, IEEE Electron Device Lett., 28, 935 (2007).
[35] K. Y. Lee, Y. J. Lee, P. Chang, M. L. Huang, Y. C. Chang, M. Hong,and J. Kwo, “Achieving 1 nm capacitive effective thickness in atomic layer deposited HfO2 on In0.53Ga0.47As”, Appl. Phys. Lett., 92, 25908 (2008).
[36] H. C. Chiu, L. T. Tung, Y. H. Chang, Y. J. Lee, C. C. Chang, J. Kwo,and M. Hong, “Achieving a low interfacial density of states in atomic layer deposited Al2O3 on In0.53Ga0.47As”, Appl. Phys. Lett., 93, 202903 (2008).

(Chapter 2)
[1] http://en.wikipedia.org/Atomic_layer_deposition
[2] Agilent 4156C, Application Note 4156-10, “Evaluation of Gate Oxides Using a Voltage Step Quasi-Static CV Method”.
[3] E. H. Nicollian and J.R. Brews, “MOS (Metal Oxide Semiconductor) Physics and Technology”, (Wiley-Interscience, Hoboken, N.J.) 2003.
[4] D. K. Schroder, “Semiconductor Material and Device Characterization”, (John Wiley, Hoboken, N.J.) 2005.
[5] L. M. Terman, “An Investigation of Surface States at a Silicon Silicon Oxide Interface Employing Metal Oxide Silicon Diodes”, Solid-State Electron., 5, 285 (1962).

(Chapter 3)
[1] Z. Tang, H. Hsia, H. C. Kuo, D. Caruth, G.E. Stillman, and M. Feng, “188 GHz doped-channel In0.8Ga0.2P/In0.53 Ga0.47As/InP HFETs”, Electron. Lett., 36, 1657 (2000).
[2] J.H. Jang, S. Kim, and I. Adesida, “Fabrication and characterization of In0.52Al0.48As/In0.53Ga0.47As E/D-HEMTs on InP substrates”, Solid-State Electron., 50, 758 (2006).
[3] T. W. Kim, S. J. Jo, and J. I. Song, “A Capless InP/In0.52Al0.48As/In0.53Ga0.47As p-HEMT Having a Self-Aligned Gate Structure”, IEEE Electron Device Lett., 27, 722 (2006).
[4] F. Ren, J. M. Kuo, M. Hong, W. S. Hobson, J. R. Lothian, J. Lin, H. S. Tsai, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, “Ga2O3(Gd2O3)/InGaAs enhancement-mode n-channel MOSFETs”, IEEE Electron Device Lett., 19, 309 (1998).
[5] Y. Xuan, Y. Q. Wu, and P. D. Ye, “High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm”, IEEE Electron Dev. Lett., 29, 294 (2008).
[6] T. D. Lin, H. C. Chiu, P. Chang, L. T. Tung, C. P. Chen, M. Hong, J. Kwo, W. Tsai, and Y. C. Wang, “High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3/ Ga2O3(Gd2O3) as gate dielectrics”, Appl. Phys. Lett., 93, 033516 (2008).
[7] M. Hong, J. P. Mannaerts, J. E. Bowers, J. Kwo, M. Passlack, W. Y. Hwang, and L. W. Tu, “Novel Ga2O3(Gd2O3) passivation techniques to produce low Dit oxide-GaAs interfaces”, J. Crystal Growth, 175/176, 422 (1997).
[8] M. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, “Epitaxial Cubic Gadolinium Oxide as a Dielectric for Gallium Arsenide Passivation”, Science, 283, 1897 (1999).
[9] P. D. Ye, G. D. Wilk, B. Yang, J. Kwo, H.-J. L. Gossmann, M. Hong, K. K. Ng, and J. Bude, “Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition”, Appl. Phys. Lett., 84, 434 (2004).
[10] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, “Surface passivation of III-V compound semiconductors using atomic-layer-deposition-grown Al2O3”, Appl. Phys. Lett., 87, 252104 (2005).
[11] M. L. Huang, Y. C. Chang, C. H. Chang, T. D. Lin, J. Kwo, T. B. Wu, and M. Hong, “Energy-band parameters of atomic-layer-deposition Al2O3/InGaAs heterostructure”, Appl. Phys. Lett., 89, 012903 (2006).
[12] Y. Xuan, Y. Q. Wu, H. C. Lin, T. Shen, and P. D. Ye, “Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric”, IEEE Electron Device Lett., 28, 935 (2007).
[13] Y. C. Chang, M. L. Huang, K. Y. Lee, Y. J. Lee, T. D. Lin, M. Hong, J. Kwo, T. S. Lay, C. C. Liao, and K. Y. Cheng, “Atomic-layer-deposited HfO2 on In0.53Ga0.47As Passivation and energy-band parameters”, Appl. Phys. Lett., 92, 072901 (2008).
[14] K. Y. Lee, Y. J. Lee, P. Chang, M. L. Huang, Y. C. Chang, M. Hong , and J. Kwo, “Achieving 1 nm capacitive effective thickness in atomic layer deposited HfO2 on In0.53Ga0.47As”, Appl. Phys. Lett., 92, 252908 (2008).
[15] S. Koveshnikov, N. Goel, P. Majhi, H. Wen, M. B. Santos, S. Oktyabrsky, V. Tokranov, R. Kambhampati, R. Moore, F. Zhu, J. Lee, W. Tsai, “In0.53Ga0.47As based metal oxide semiconductor capacitors with atomic layer deposition ZrO2 gate oxide”, Appl. Phys. Lett., 92, 222904 (2008).
[16] D. G. Park, H. J. Cho, K. Y. Lim, C. Lim, I. S. Yeo, J. S. Roh, and J. W. Park, “Characteristics of n+ polycrystalline-Si/Al2O3/Si metal-oxide-semiconductor structures prepared by atomic layer chemical vapor deposition using Al(CH3)3 and H2O vapor”, J. Appl. Phys., 89, 6275 (2001).
[17] I. S. Jeon, J. Park, D. Eom, C. S. Hwang, H. J. Kim, C. J. Park, H. Y. Cho, J. H. Lee, N. I. Lee and H. K. Kang, “Post-Annealing Effects on Fixed Charge and Slow/Fast Interface States of TiN/Al2O3/p-Si Metal-Oxide-Semiconductor Capacitor”, Jpn. J. Appl. Phys., 42, 1222 (2003).
[18] D. M. Fleetwood, P. S. Winokur, R. A. Reber, Jr., T. L. Meisenheimer, J. R. Schwank, M. R. Shaneyfelt, and L. C. Riewe, “Effects of oxide traps, interface traps, and “border traps” on metal-oxide-semiconductor devices”, J. Appl. Phys., 73, 5058 (1993).
[19] Y. Sun, P. Pianetta, P. T. Chen, M. Kobayashi, Y. Nishi, N. Goel, M. Garner, and W. Tsai, “Arsenic-dominated chemistry in the acid cleaning of InGaAs and InAlAs surfaces”, Appl. Phys. Lett., 93, 194103 (2008).
[20] K. Martens, C. O. Chui, G. Brammertz, B. D. Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes, and G. Groeseneken, “On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates”, IEEE Trans. Electron Device, 55, 547 (2008).
[21] E. H. Nicollian and J.R. Brews, “MOS (Metal Oxide Semiconductor) Physics and Technology”, (Wiley-Interscience, Hoboken, N.J.) 2003.
[22] Agilent 4156C, Application Note 4156-10, “Evaluation of Gate Oxides Using a Voltage Step Quasi-Static CV Method”
[23] C. N. Berglund, “Surface States at Steam-Grown Silicon-Silicon Dioxide Interfaces”, IEEE Trans. Electron Devices, 13, 701 (1966).
[24] G. Brammertz,H. C. Lin, M. Caymax, M. Meuris, M. Heyns, and M. Passlack, “On the interface state density at In0.53Ga0.47As/oxide interfaces”, Appl. Phys. Lett., 95, 202109 (2009).
[25] K. Martens, B. Kaczer, H. Maes, and G. Groeseneken, Intl. SiGe Tech. and Device. Meet. 2008, 82-83.
[26] G. V. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, IEEE Trans. Electron Devices, 31, 42, (1984).
[27] D. Bauza and Y. Maneglia, IEEE Trans. Electron Devices, 44, 2262, (1997).
[28] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, Appl. Phys. Lett. 87, 252104 (2005).
[29] M. L. Huang, Y. C. Chang, C. H. Chang, T. D. Lin, J. Kwo, T. B. Wu, and M. Hong, Appl. Phys. Lett. 89, 012903 (2006).
[30] S. Jakschik, A. Avellan, U. Schroeder, and J. W. Bartha, IEEE Trans. Electron Devices, 51, 2252, (2004).

(Chapter 4)
[1] M. Hong, J. P. Mannaerts, J. E. Bowers, J. Kwo, M. Passlack, W. Y. Hwang, and L. W. Tu, “Novel Ga2O3(Gd2O3) passivation techniques to produce low Dit oxide-GaAs interfaces”, J. Crystal Growth, 175/176, 422 (1997).
[2] F. Ren, J. M. Kuo, M. Hong, W. S. Hobson, J. R. Lothian, J. Lin, H. S. Tsai, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, “Ga2O3(Gd2O3)/InGaAs Enhancement-Mode n-Channel MOSFET’s,” IEEE Electron Device Lett., 19, 309 (1998).
[3] Y. Xuan, Y. Q. Wu, and P. D. Ye, “High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1A/mm,” IEEE Electron Device Lett., 29, 294 (2008).
[4] T. D. Lin, H. C. Chiu, P. Chang, L. T. Tung, C. P. Chen, M. Hong, J. Kwo, W. Tsai, and Y. C. Wang, “High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3/ Ga2O3(Gd2O3) as gate dielectrics”, Appl. Phys. Lett., 93, 033516 (2008).
[5] Y. Xuan, P. D. Ye and T. Shen, “Substrate engineering for high-performance surface-channel III-V metal-oxide-semiconductor field-effect transistors”, Appl. Phys. Lett., 95, 202109 (2009).
[6] D. Shahrjerdi, T. Akyol, M. Ramon, D. I. Garcia-Gutierrez, E. Tutuc, and S. K. Banerjee, “Self-aligned inversion-type enhancement-mode GaAs metal-oxide- semiconductor field-effect transistor with Al2O3 gate dielectric,” Appl. Phys. Lett., 92, 203505 (2008).
[7] J. Q. Lin, S. J. Lee, H. J. Oh, G. Q. Lo, D. L. Kwong, and D. Z. Chi, “ Inversion-Mode Self-Aligned In0.53Ga0.47As N-Channel Metal-Oxide-Semiconductor Field- Effect Transistor With HfAlO Gate Dielectric and TaN Metal Gate,” IEEE Electron Device Lett., 29, 977 (2008).
[8] J. P. de Souza, E. Kiewra, Y. Sun, A. Callegari, D. K. Sadana, G. Shahidi, D. J. Webb, J. Fompeyrine, R. Germann, C. Rossel, and C. Marchiori, “Inversion mode n-channel GaAs field effect transistor with high-k/metal gate,” Appl. Phys. Lett., 92, 153508 (2008).
[9] A. M. Sonnet, C. L. Hinkle, M. N. Jivani, R. A. Chapman, G. P. Pollack, R. M. Wallace, and E. M. Vogel, “Performance enhancement of n-channel inversion type InxGa1-xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer,” Appl. Phys. Lett., 93, 122109 (2008).
[10] H. C. Chin, M. Zhu, C. H. Tung, G. S. Samudra, and Y. C. Yeo, “In-situ Surface Passivation and CMOS-Compatible Palladium-Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs,” IEEE Electron Device Lett., 29, 553 (2008).
[11] F. Fracassi, R. d’Agostino, R. Lamendola, and I. Mangieri, “Dry etching of titanium nitride thin films in CF4–O2 plasmas “, J. Vac. Sci. Technol. A, 13, 335 (1995).
[12] R. d’Agostino, F. Fracassi, C. Pacifico, and P. Capezzuto, “Dry etching of Ti in chlorine containing feeds”, J. Appl. Phys., 71, 462(1992).
[13] J. Tonotani, T. Iwamoto, F. Sato, K. Hattori, S. Ohmi, and H. Iwai, “Dry etching characteristics of TiN film using Ar/CHF3, Ar/Cl2, and Ar/BCl3 gas chemistries in an inductively coupled plasma”, J. Vac. Sci. Technol. B, 21, 2163 (2003).
[14] C. T. Gabriel, J. Zheng, and S. C. Abraham, “Minimizing metal etch rate pattern sensitivity in a high density plasma etcher”, J. Vac. Sci. Technol. A, 15, 697 (1997).
[15] S. C. Abraham, C. T. Gabriel, and J. Zheng, “Performance of different etch chemistries on titanium nitride antireflective coating layers and related selectivity and microloading improvements for submicron geometries obtained with a high-density metal etcher”, J. Vac. Sci. Technol. A, 15, 702 (1997).
[16] Y. Xuan, Y. Q. Wu, H. C. Lin, T. Shen, and P. D. Ye, “Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric”, IEEE Electron Device Lett., 28, 935 (2007).
[17] Y. Xuan, Y. Q. Wu, T. Shen, T. Yang, and P. D. Ye, “High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics”, in Int. Electron Devices Meeting Tech. Dig., 2007, 637.
[18] Y. Taur, “MOSFET Channel Length: Extraction and Interpretation”, IEEE Trans. Electron Devices, 47, 160 (2000).
[19] http://www.srim.org/
[20] Y. Xuan, H. C. Lin, P. D. Ye, and G. D. Wilk, “Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric”, Appl. Phys. Lett., 88, 263518 (2006).
[21] C. P. Chen, T. D. Lin, Y. J. Lee, Y. C. Chang, M. Hong, and J. Kwo, “Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal-oxide-semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric”, Solid-State Electron, 52, 1615 (2008).
[22] Y. Xuan, T. Shen, M. Xu, Y. Q. Wu, and P. D. Ye, “High-performance Surface Channel In-rich In0.75Ga0.25As MOSFETs with ALD High-k as Gate Dielectric”, in Int. Electron Devices Meeting Tech. Dig., 2008, 371.
[23] Y. Q. Wu, W. K. Wang, O. Koybasi, D. N. Zakharov, E. A. Stach, S. Nakahara,J. C. M. Hwang, and P. D. Ye, “0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode In0.75Ga0.25As MOSFET”, IEEE Electron Device Lett., 30, 700 (2009).
[24] R. Chau, S. Datta, and A. Majumdar, “Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications”, in IEEE CSIC Symp. Tech. Dig., 2005, 17.
[25] S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, “Design and Characteristics of the Lightly Doped Drain-Source (LDD) insulated Gate Field-Effect Transistor”, IEEE Trans. Electron Devices, 27, 1359 (1980).
[26] S. M. Sze and K. K. Ng, “Physics of semiconductor devices” (Wiley-Interscience, N. J., 3rd ed. 2007).

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