本篇論文透過分析指令使用處理器管線資源的情況，為亂序處理器提出一個高效能的時序模型。目前為處理器建構的時序模型往往只擁有高效能或高時脈精準度其一優點。其中擁有高時脈精準度的時序模型，透過詳細的微架構分析達到了時脈精準度的目標，但低效能的特性使得它們不適用於系統層級模擬。我們透過精準並有效的抓出指令與處理器管線中被使用的資源兩者互動的時間點，來達到高時脈精準度與高效能的雙重目標。實驗數據顯示我們所提出的「指令導向」模擬方法，其模擬效能擁有不錯的延展性，同時也具備高度的時脈精準度。和既有最普遍的時脈精準的模擬方法比較，受測的軟體在資源較差的目標管線內執行，我們的模擬方法效能遞減的幅度比既有方法減少了四倍之多。

In this paper we propose a highly efficient timed model for pipelined out-of-order processors based on resource usage analysis. Existing timed processor models either are limited to simple processor architectures or are inefficient for system simulation purpose as they require detailed micro-architecture analysis. By capturing the timing of resource availability changes in the proposed instruction-oriented simulation algorithm, the cycle counts of programs executed on the target processors can be accurately and efficiently computed. The experimental results show excellent performance scalability and accuracy of the proposed instruction-oriented approach for processor architecture explorations. For processor models with increased cycle counts, the proposed approach incurs four times less overhead than the CA approach.

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