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研究生: 林昌博
Chang-Po Lin
論文名稱: 熱能限制下的晶片堆疊規劃
Chip Stacking in SiP Designs under Thermal Constraint
指導教授: 黃婷婷
TingTing Hwang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 35
中文關鍵詞: 晶片堆疊熱能限制
外文關鍵詞: SiP
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  • 隨著製成的進步,晶片及匯流排間的評寬需求量越來越大,但是封裝技術的進步已經不再能夠滿足這種需求了,並且這種需求的鴻溝越來越大。在另一方面,將系統整合在同一個晶片的需求也越來越大,其中一種解決方法就是System-on-Package(SOC)。但是因為要將不同製程的的晶片整合在單一晶片的難度非常高,導致SOC的良率非常的低。為了因應頻寬以及整合上的需求,System-in-Package(SiP)技術就被發展出來了。基本的SiP概念就是將每個晶片在最適合它的製成下製造完成後再使用封裝技術將不同的晶片整合在同一個封裝內。
    在之前的研究中,我們看到有關於如何在三度空間的考量下對晶片做樓層規劃並且同時考量熱能的產生的研究。也有看到有關如何將晶片堆疊及旋轉規劃並且解決晶片間的繞線的問題的研究。卻沒有看到可以同時解決熱能問題以及規劃晶片堆疊以及旋轉的研究存在。
    在本篇論文中,我們將會展示一個應用在SiP技術且非常有效率並且可以考量到過熱問題的晶片堆疊規劃產生器,以及能夠有效的減少底層PCB版繞線層數的使用量的底層繞線機。我們的演算法可以分成兩個階段,首先我們會將晶片堆疊起來,並確保沒有違反封裝場的設計限制以及沒有違反使用者的熱能限制。在第二個階段時,我們將會把晶片間對應的連接線接起來,並且將底層PCB版的使用層數降到最低。


    In this thesis, we will present an e®ective thermal-aware chip stacking planner and a
    leadframe router to reduce the number of wiring layers in SiP designs. Our algorithm is
    conducted in two stages. In the ‾rst stage, we place each of bare dies to a feasible location
    and make sure that they do not violate the design rule and thermal constraints. In the
    second stage, we route the interconnection of stacked dies so that the routing resource is
    minimized.

    Contents 1 Introduction 1 2 Problem De‾nition and Background 3 2.1 Overview of System-in-Package and Problem De‾nition . . . . . . . . . . . . 3 2.2 Wiring in SiP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.2 Connect Through Leadframe . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Design Rule of SiP Connection and Stacking . . . . . . . . . . . . . . . . . . 5 2.3.1 Stacking Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.2 Connection Rule 1: No Direct Connection between Two Pads Located at the Di®erent Sides . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.3 Connection Rule 2: No Cross Wire . . . . . . . . . . . . . . . . . . . 7 2.3.4 Shading E®ect of Successive Equally Sized Dies . . . . . . . . . . . . 8 2.4 Routing in Leadframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Algorithm Descriptions 11 3.1 Overview of Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Thermal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Direct SiP Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Leadframe Routing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.2 Initial Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.3 Rip up and Reroute . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.4 Layer Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Experimental Results 29 4.1 Chip Stacking and Rotation under Thermal Constraint . . . . . . . . . . . . 29 4.2 Leadframe Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Conclusions 33 i List of Figures 1.1 Growing gap between packaging and fabrication. . . . . . . . . . . . . . . . . 1 1.2 In high system complexity design, SiP is a more e±cient solution. . . . . . . 2 2.1 SiP stacking structure inter-die connection being connected directly or through leadfreame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 (a)(b)Two pads on di®erent dies with the same side can be connected directly. (c)Connections violate design rule and are connected through leadframe. . . 5 2.3 One spacer die between two equally sized dies. die1 cannot connect to any dies above die2 because of the blockage of die2. . . . . . . . . . . . . . . . . 6 2.4 Pads at di®erent sides are not allowed connected directly. . . . . . . . . . . . 7 2.5 (a)Crossed wires are not allowed. (b)Some wire is routed through leadframe. 8 2.6 This 3-terminal net is consist of 3 wire segments, 2 for horizontal, 1 for vertical. ­ is a candidate location of via . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 The °ow chart of our algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Wiring selection from cross wire set of spanning trees. . . . . . . . . . . . . . 14 3.3 The °ow chart of leadframe routing . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 The °ow chart of initial route. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 (a)Connection of net1 is a shape of stair. It is the shortest path and introduces 2 bends. (b)Same stair shape with less congestion. . . . . . . . . . . . . . . . 17 3.6 (a)Connection of net1 is a shape of shoe. It is the shortest path and introduces 2 bends. (b)To avoid congested area, the path is longer. . . . . . . . . . . . 18 3.7 (a)To connect 2 terminals of net1, shape of corner is shortest and only intro- duce 1 bends. (b)To avoid congested area, the bends have to increase by 2 at least. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 (a) 3 shoe-shape net to be connected. Gray area is pre-routed by net1.(b) Bad result of connecting net2 without considering average congestion. (c) Better result of connecting net2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 (a)(b)(c) Evaluating the congestion of each pair of multi-terminal net, net1, we drop the corner route from 10 to 100 which is most congested. (d)Route remaining pairs in clockwise order. (e)Route starts from 100 and end until it meets the wire in (d). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 The °ow chart of rip up and reroute . . . . . . . . . . . . . . . . . . . . . . 23 3.11 (a)Cost of grids. S is source and T is destination. * means unreachable. (b)The path with cost 16 has to drop. (c)A bend increases the cost. (d)Cost of grids in graph-to-graph router. . . . . . . . . . . . . . . . . . . . . . . . . 25 ii 3.12 (a)Initial route of net1 and congestion area is marked by gray. (b)Bad reroute if rip up wrong wires. (c)Rip up entire wire. (d)Nice result of a graph-to-graph router. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 Example of feasible move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 iii List of Tables 4.1 Con‾gurations of HotSpot . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 Number of leadframe under di®erent temperature constraints. . . . . . . . . 31 4.3 Leadframe router comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 Leadframe router statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

    Bibliography
    [1] Albert W. Lin, \Taiwan Foundry for System-In-Package (SIP)," Asia-South Paci‾c
    Design Automation Conference, 2000.
    [2] Jani Miettinen, Matti Mantysalo, Kimmo Kaija, and Eero O. Ristolainen, \System
    Design Issues for 3D System-in-Package (SiP)," Electronic Components and Technology
    Conference, 2004.
    [3] Jason Cong, Jie Wei, and Yan Zhang, \A Thermal-Driven Floorplanning Algorithm for
    3D ICs," International Conference on Computer Aided Design, 2003.
    [4] Shin-Chuan Lai, and Chung-Haw Wu, \A Leadframe Minimization Method for System-
    In-Package", MS thesis, National Tsing Hua University, 2005.
    [5] W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan, \HotSpot:
    Thermal Modeling for CMOS VLSI Systems," IEEE Transactions on Component Pack-
    aging and Manufacturing Technology, 2005.
    [6] J. P. Cohoon and P. L. Heck, \BEAVER: A computational-geometrybased tool for
    switchbox routing," IEEE Transactions on Computer-Aided Design, vol. 7, no. 6, pp.
    684V697, 1988.
    [7] Y. Shin and A. Sangiovanni-Vincentelli, MIGHTY: A rip-up and reroute detailed router,
    Proc. Int. Conf. Computer-Aided Design, 1986, pp. 2-5.
    [8] R. Joobbani, \Weaver: A knowledge-based routing expert," Carnegie-Mellon Univ., Res
    Rep. CMUCAD-85-86, June 1985.
    34
    [9] N. Gockel, R. Drechsler and B. Becker, \A Multi-Layer Detailed Routing Approach
    based on Evolutionary Algorithms," Proc. of IEEE International Conference on Evo-
    lutionary Computation, Proc. of the IEEE Int. Conf. on Evolutionary Computation,
    Indimapolis, IN, U.S.A., pp. 557-562
    [10] Lee, \An algorithm for path connection and its application," IRE Transactions on
    Electronic Computer, EC-10, 1961.
    [11] Y.-C. Chou and Y.-L. Lin, \A graph-partitioning-based approach for multi-layer con-
    strained via minimization," Proc. IEEE/ACM International Conference on Computer-
    Aided Design, pp. 426-429, 1998.
    [12] A. Mehrotra and M. A. Trick, \A column generation approach for graph coloring,"
    INFORMS Journal on Computing, vol. 8, no. 4, pp. 344{354, 1996.
    [13] Rao R. Tummala, \Fundamentals of microsystems packageing," pp. 73, 2001.
    [14] Fraunhofer Institute for Reliability and Microintegration IZM

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