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研究生： 葉凌彥
Yeh, Ling-Yen
論文名稱： 應用於金氧半電晶體的鋁酸鑭閘極介電層及應變矽技術之研究
LaAlO3 Gate Dielectric and Strained Silicon Technologies for Metal-Oxide-Semiconductor Field Effect Transistor Applications
指導教授： 葉鳳生
Yeh, Fon-Shan
李雅明
Lee, Joseph Ya-Min
口試委員:
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 98
中文關鍵詞： 高介電常數介電質 、閘極氧化層 、應變矽 、鋁酸鑭 、金氧半電晶體
外文關鍵詞： high-k dielectric, gate dielectric, strained silicon, LaAlO3, MOSFET
相關次數： 點閱：2  下載：0 
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    • 自從1958年, 全世界第一個積體電路 (integrated circuit) 問世以來，今天的積體電路已經廣泛影響到人類的日常生活，並且大量的應用於電腦運算、通訊系統、影音處理、交通運輸、醫療設備等項目。大部份的積體電路都是由矽金氧半電晶體 (silicon metal-oxide-semiconductor field-effect transistor) 所組成的。隨著技術的演進，金氧半電晶體的尺寸可以縮小，因此單位面積的電晶體數目會隨之增多。
    1960年代初期高登摩爾 (Gordon Moore) 預測單位面積的電晶體數目每十八到二十四個月會增加一倍。當金氧半電晶體的通道長度小於約五十奈米時，要繼續跟隨摩爾定律的預測，最需要解決兩個問題，其一是如何用高介電常數介電層取代傳統的二氧化矽以降低閘極漏電流，其二是如何使載子在通道的遷移率藉由應變而增加，進而增加元件的速度。因此，這篇論文就以這兩個問題為主軸，對高介電常數鋁酸鑭介電層 (high dielectric constant LaAlO3 gate dielectric) 的可靠度及應變矽 (strained silicon) 效應隨通道尺寸的變化做研究和探討。
    在論文的第一部份，高介電常數鋁酸鑭介電層的可靠度，我們製作了以鋁酸鑭為閘極介電層的n 型電容器和金氧半電晶體。量測鋁酸鑭介電層的元件可靠度包括定電壓下的介電層崩潰 (time dependent dielectric breakdown)、定電壓下介電層崩潰前漏電流隨時間的變化 (stress induced leakage current) 和臨界電壓 (threshold voltage) 在閘極正偏壓下隨時間的變化 (positive bias temperature instability)，並研究其中的物理機制。
    在論文的第二部份，我們以高張應力 (tensile stress) 的氮化矽作為產生通道矽應變 (channel strain) 的來源。計算在此薄膜應力下傳送到通道的應力並比較通道應力在各種不同通道長度 (channel length) 和寬度 (channel width) 下的變化。並根據不同的載子傳輸 (carrier transport) 機制分別計算出通道電流的改變，與實際量測的結果做比較。以此判斷不同傳輸機制在各種不同通道長度和寬度下的影響。

    Since the first integrated circuit was created in 1958, the integrated circuit technology has widely influenced our daily life. This technology has been applied to various modern electronic devices such as computers, mobile phones, audio and video devices, medical electronics and so on. The major component of the integrated circuit is the transistor and most of the transistors used today are the metal-oxide-semiconductor field-effect transistors (MOSFETs). With the progress of process technology, the dimension of transistors shrinks and therefore the number of transistors per unit area increases in the integrated circuits accordingly. At the beginning of 1960’s, Gordon Moore forecasted that the numbers of transistors per unit area will double every eighteen to twenty four months. It becomes more difficult to follow Moore’s law when the channel length of MOSFETs shrinks below 50 nm. The two major issues of further scaling are the following, first, the appropriate high-dielectric-constant thin film to replace the traditional silicon dioxide and, secondly, the mobility of carriers in the channel needs to be enhanced by strained silicon. Therefore, this thesis focuses on these two issues. The first part of the thesis describes the reliability properties of LaAlO3 gate dielectric and the second part on the modeling of nMOSFET with strained silicon.
    In the first part of this thesis, MOS capacitors and nMOSFETs with LAO gate dielectric were fabricated and various reliability properties, including time dependent dielectric breakdown, stress induced gate leakage current and positive bias temperature instability, were all studied.
    In the second part of the thesis, strained n-channel MOSFETs with various channel widths and lengths were fabricated and the stresses in the channel were simulated. The enhancement of the on-state drain current in the channel was then calculated by the simulated stress in the channel and compared to the measured data.

    Contents Pages Abstract iii Acknowledgement v List of tables viii List of figures ix Chapter 1 Introduction of nanometer-scale CMOS devices 1.1 Technology roadmap of CMOS transistors 1 1.2 Application of high-k□ dielectric to MOSFETs 5 1.3 Strained MOSFETs 12 1.4 Outline of the thesis 13 Chapter 2 Fabrication of MOS capacitors and nMOSFETs with LaAlO3 gate dielectric 2.1 Deposition of LaAlO3 dielectric 17 2.2 Fabrication of MOS capacitors with LaAlO3 gate dielectric 18 2.3 Fabrication of nMOSFETs with LaAlO3 gate dielectric 22 Chapter 3 Physical and electrical properties of MOS capacitors and nMOSFETs with LaAlO3 gate dielectric 3.1 Physical properties of MOS capacitors and nMOSFETs with LaAlO3 gate dielectric 23 3.2 Electrical properties of MOS capacitors and nMOSFETs wth LaAlO3 gate dielectric 27 3.3 Electron mobility of nMOSFETs with LaAlO3 gate dielectric 31 Chapter 4 Time dependent dielectric breakdown of MOS capacitors with LaAlO3 gate dielectric 4.1 Modeling of time dependent dielectric breakdown 35 4.1.1 E model 35 4.1.2 1/E model 36 4.2 Time dependent dielectric breakdown of MOS capacitors with LaAlO3 gate dielectric 37 Chapter 5 High-voltage stress-induced leakage current of MOS capacitors with LaAlO3 dielectric 5.1 Introduction of chapter 5 45 5.2 Results and discussion 45 Chapter 6 Positive bias temperature instability of nMOSFETs with LaAlO3 gate dielectric 6.1 Introduction to bias temperature instability of nMOSTET with LaAlO3 gate dielectric 50 6.2 Positive bias temperature instability of LaAlO3 nMOSFETs with LaAlO3 gate dielectric 51 6.2.1 Electrical stress-induced defect generation (ESIDG) in the interfaciallayer 57 6.2.2 Oxygen vacancy induced electron trapping in LaAlO3 gate dielectric 58 Chapter 7 Modeling of the on-state current enhancement of strained nMOSFETs 7.1 The dependence of the performance of strained nMOSFETs on channel width 60 7.1.1 Calculation of effective mass 61 7.1.2 Calculation of energy band structure using k•p model 62 7.2 The dependence of the performance of strained nMOSFETs on channel length 71 Chapter 8 Conclusion and future study 79 Reference 82 Publication List 96

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