在鎖相迴路的自我測試電路中，時脈抖動的量測是一個很重要的項目，而量測的精確度則是依據正反器的錯誤區域而定的。在這裡錯誤區域的定義為保持時間跟設定時間的總和，也就是在時脈觸發時，資料輸入訊號必須保持穩定的時間。 本篇論文提出了一種基於單向位時序技術的資料正反器，此種正反器包含能讓正反器有確切預設值的設置與重設的功能和一個能改進因漏電流造成動態架構正反器操作錯誤的回授電路。為了要與標準元件庫的正反器在實際下線的效能作比較，本論文設計了一種基於欠採樣原理的測試電路，並且也設計一個測試板來增加實際量測時的準確性。在基於0.13微米製程的模擬結果中，本論文提出的正反器擁有大約比標準正反器還小60%的錯誤區域與大約短55%的內在延遲時間。但在實際量測測試電路時，因為設計電路時考量的不夠周全與輸入時脈的雜訊與模擬時差距太大，導致量測結果只有一部分符合模擬結果。
在一些超低功率消耗的應用上，讓電晶體在次臨界區域的操作是比較被推薦的。本篇論文使用兩種不同的分析方式來比較提出的正反器與其他正反器在次臨界區域的效能，包含了能模擬電路在穩定狀態下的直流分析與能模擬出正反器錯誤區域與延遲的暫態分析。如此一來便可提出在次臨界區域操作時建議的正反器架構給不同的應用。然而在次臨界區域時，電晶體的操作原理並不相同，所以導致電流產生的原理不同。為了要在次臨界區域也擁有最佳的效能，本篇論文提出一種最佳化電晶體尺寸的方法來找出提出的正反器在次臨界區域擁有最小錯誤區域的電晶體尺寸。在最佳化後，當供給電壓從0.20伏特掃描至0.30伏特時，提出的正反器擁有平均比標準正反器縮小大約90%的錯誤區域。

Jitter measurement is an important issue of PLL BIST (Build-In-Self-Test), and the accuracy of jitter measurement is dependent on deadzone of DFFs, which is the summation of setup time and hold time. This thesis developed DFFs based on TSPC (True Single Phase Clock) technique. The proposed DFFs includes Set/Reset function in order to allow preset initial values for digital design, and feedback structures were added to improve low frequency operation which is a weakness of dynamic DFF structure. To verify the on-chip performance of these proposed DFFs and to compare with standard cell library DFFs, a test circuit based on under-sampling method had been designed, and a test board had also been designed and implemented for the accurate on-chip measurement. The simulation results, obtained from a 0.13 um technology, show about 60% deadzone and 55% intrinsic delay improvements over the standard cell library DFFs. The test circuit is partial work during on-chip measurement because there has some incorrect design in test circuit and the noises of clock signals are much larger than SPEC which decreasing the resolution and causing the failed results.
For ultra-low power applications, sub-threshold region operation is preferred. This thesis analyzes different types of DFF with proposed DFFs to compare deadzone, delay with DC analysis which could provide a steady state simulation and a transient analysis which could simulate the actually performance. Thus recommendations on DFF structures in different application will be developed. Due to operating theory of MOSFETs are different between subthreshold region and normal region, an optimal method which could find an optimal size of proposed DFFs is also mentioned. And the performance of optimal proposed DFFs have a huge improvement of deadzone with standard DFFs which is about 90% in average when supply voltage sweep from 0.20V to 0.30V.

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