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研究生: 周沛毅
Chou, Pei-Yi
論文名稱: 適用於多用戶多輸入多輸出下鍊之基於迫零髒紙編碼預編碼器設計與實作
Design and Implementation of Precoder Based on Zero-Forcing Dirty Paper Coding for MU-MIMO Downlink
指導教授: 黃元豪
Huang, Yuan-Hao
口試委員: 沈中安
Shen, Chung-An
陳坤志
Chen, Kun-Chih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 通訊工程研究所
Communications Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 英文
論文頁數: 91
中文關鍵詞: 多輸入多輸出預編碼髒紙編碼
外文關鍵詞: MIMO, precoding, ZF-DPC
相關次數: 點閱:123下載:0
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  • 第五代通訊系統中使用Sub-6和毫米波兩個頻段。其中毫米波頻段的電磁波
    波長較短,所以適合使用巨型陣列天線技術滿足現代通訊高吞吐量的傳送需求。
    本論文的研究鎖定巨型陣列天線下,下行多用戶的通訊情境。在下行多用戶的通
    訊情境中,迫零髒紙編碼預編碼演算法具有最大的通道容量,以及在傳送天線個
    數和接收天線個數相同時具有最低的複雜度。因此在此論文中,我們設計迫零髒
    紙編碼預編碼器的電路,並且採用水填充法進行功率分配,以最大化通訊系統通
    道容量。最後,透過28 nm製程,實現出迫零髒紙編碼預編碼器,在151 MHz
    時鐘速度下,可以達到19.25 Gbps的資料吞吐量,以及147K matrices/s的通道
    更新率。


    Both the Sub-6 GHz and millimeter-wave (mmWave) frequency bands are utilized in the fifth-generation (5G) communication system. Due to the shorter wavelength of electromagnetic waves in the mmWave band, massive antenna array technology is well-suited to meet the high-throughput transmission demands of modern communication. This thesis focuses on the downlink multi-user communication scenario under antenna arrays. In such a scenario, the zero-forcing dirty paper coding (ZF-DPC) precoding algorithm achieves the highest channel capacity and the lowest complexity when the number of transmit and receive antennas is equal. Therefore, in this thesis, we design a circuit for the ZF-DPC precoder and employ the water-filling method for power allocation to maximize the channel capacity of the communication system. Finally, using a 28nm process, we implement the ZF-DPC precoder, which achieves a data throughput of 19.25 Gbps and a channel update rate of 147K matrices/s at a clock speed of 151 MHz.

    1 Introduction 1 1.1 Multi-UserMassiveMulti-InputMulti-OutputSystems . . . . . . . . . . 1 1.2 PrecodingforMulti-userMassiveMIMO . . . . . . . . . . . . . . . . . . 2 1.3 ResearchMotivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 OrganizationofThisThesis . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Multi-UserMIMOPrecodingSystemandZero-ForcingDirtyPaper Coding 7 2.1 SystemModelofMulti-UserMIMOPrecodingSystems . . . . . . . . . . 8 2.2 Zero-ForcingDirtyPaperCoding . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 BroadcastMIMOSystemsBasedonZero-ForcingDirtyPaper Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Water-FillingPowerAllocation . . . . . . . . . . . . . . . . . . . 14 2.3 ComparisonamongDifferentDownlinkMU-MIMOAlgorithms . . . . . . 18 2.3.1 SumSpectralEfficiencyofDifferentDownlinkMU-MIMOAlgo rithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.2 ComputationalComplexityofDifferentDownlinkMU-MIMOAl gorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.3 SimulationResults . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3 Zero-ForcingDirtyPaperCodingPrecoderHardwareDesign 39 3.1 OutlineofZF-DPCPrecoderCircuits . . . . . . . . . . . . . . . . . . . . 39 3.2 HardwareDesignofQRDProcessorinZF-DPCPrecoder . . . . . . . . . 40 3.2.1 SystolicArrayandProcessingElementsforQRDProcessor. . . . 40 3.2.2 MinimalLatencyofQRDProcessor . . . . . . . . . . . . . . . . . 45 3.2.3 HardwaredesignofQRMemory. . . . . . . . . . . . . . . . . . . 48 3.2.4 FoldingonQRDProcessor . . . . . . . . . . . . . . . . . . . . . . 50 3.3 TheMethodtoReducingThePENumberofQRDProcessor. . . . . . . 54 3.3.1 Zero-ElementPropertyofQRDProcessor . . . . . . . . . . . . . 55 3.3.2 TheAlgorithmforSearchingZero-ElementIntervals. . . . . . . . 56 3.3.3 ReductionofTheNumberofProcessingElementsinQRDProcessor 57 3.4 HardwareDesignofDataProcessor . . . . . . . . . . . . . . . . . . . . . 62 3.4.1 HardwareDesignofPowerAllocator . . . . . . . . . . . . . . . . 63 3.4.2 HardwareDesignofCoefficientCalculator . . . . . . . . . . . . . 64 3.4.3 HardwareDesignofDirtyPaperEncoder . . . . . . . . . . . . . . 66 3.4.4 HardwareDesignofMatrix-VectorMultiplier . . . . . . . . . . . 70 4 HardwareImplementationResults 73 4.1 OverallPrecoderArchitecture . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1.1 VLSIArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1.2 Fixed-PointSimulationResults . . . . . . . . . . . . . . . . . . . 75 4.1.3 TimingSchedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2 QRDProcessorandQRmemory . . . . . . . . . . . . . . . . . . . . . . 78 4.2.1 VLSIArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.2 TimingSchedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.3 ImplementationResults . . . . . . . . . . . . . . . . . . . . . . . 79 4.3 PowerAllocatorandDirtyPaperCodingCoefficientCalculator . . . . . 80 4.3.1 VLSIArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3.2 TimingSchedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3.3 ImplementationResults . . . . . . . . . . . . . . . . . . . . . . . 82 4.4 DirtyPaperEncoderandMatrix-vectorMultiplier . . . . . . . . . . . . . 83 4.4.1 VLSIArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.4.2 TimingSchedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.4.3 ImplementationResults . . . . . . . . . . . . . . . . . . . . . . . 84 4.5 ComparisonwithState-of-The-ArtPrecoderWorks . . . . . . . . . . . . 85 5 ConclusionandFutureWorks 87 References 89

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