在本篇論文中，將探討各種接收器架構的優劣，而相較於傳統式的超外插接收器，直接降頻接收器擁有較佳的積體化能力，同時擁有較低的功率消耗，高品質因子（Q）的被動元件，將有助於RF-SOC，進而使接收器能達到同時存在多頻段，多規格的使用。
雖然直接降頻接收擁有許多優勢，但仍存在著許多缺點，而最令人詬病的在於其架構會有直流偏移的重大缺失。本論文將改變電路架構，在傳統的低雜訊放大器及混波器之間置入一個可變增益放大器，使接收器本地震盪端到射頻端的隔絕度提升，自然直流偏移跟著下降。另外也把此放大器，利用特別的增益控制方式，加強接收器對射頻輸入訊號的動態接收範圍，同時在低增益模式也能擁有較高的線性度（P1dB＞1dBm），以接受較大訊號的輸入。
而利用BiCMOS所做的收發器（如GSM/GPRS/DCS/PCS, WLAN, Bluetooth and DECT），都已分別被發表出， 目前必須考量的一大重點即是RF-SOC（RF-system- on- chip），使能適用於多頻帶、多規格同時存在的蜂巢式系統，如圖1.2。同時，RF-SOC的雜訊干擾必須盡量減少，電路簡單、功率消耗低、成本低。而其實高頻電路設計的性能往往取決於元件層級，故在製程的選擇上顯得重要。CMOS其優點為線性度高，成本低；BJT的轉導大、功率消耗低，同時所產生雜訊亦較低[3][4]，如圖1.3。結合兩者優點，在此提出以BiCMOS SiGe製程進行電路研製。
這裡藉由tsmc所提供的SiGe 0.35um BiCMOS製程，製作相關電路，包含低雜訊放大器、可變增益放大器及混波器，並整合成一簡單的前端接收器。

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