研究生: |
廖釗漢 Liao, Chao Han |
---|---|
論文名稱: |
一個每秒取樣1.5億次以時域延遲訊號輸出數位碼之混合型連續漸進式類比數位轉換器 A 150MS/s 10bits Hybrid SAR ADC with Time-domain analysis |
指導教授: |
朱大舜
Chu, Ta Shun |
口試委員: |
吳仁銘
王毓駒 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 71 |
中文關鍵詞: | 電壓控制延遲訊號 、連續漸進式類比數位轉換器 、時間量化器 |
外文關鍵詞: | SAR ADC, Voltage Control Delay Line, Vernier Time Delay |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
中文摘要
研究所別:電機工程學系
論文名稱: 一個每秒取樣1.5億次以時域延遲訊號輸出數位碼之混合型連續漸進式類比數位轉換器
指導教授:朱大舜 博士
研究生:103061623,廖釗漢
隨著科技日新月異的發展,行動通訊對於資料傳遞的精確度以及速度上的需求更加苛刻,因此設計更快速的高速電路架構儼然已成為當代社會的趨勢。
自然界所產生的信號皆為類比型態的連續訊號,而目前許多資料處理型式為數位型態的離散訊號,因此在類比與數位訊號間,需要一個類比數位轉換器的架構來轉換兩者訊號,而當中又以連續漸進式類比數位轉換器較為廣泛運用,連續漸進式類比數位轉換器不需額外的放大器電路架構,相對其他類比數位轉換器而言,佔用較少的電路面積及擁有低功耗的優點。
本論文實現了一個每秒取樣1.5億次以時域延遲訊號輸出數位碼的十位元混合型連續漸進式類比數位轉換器,前四位元使用時域延遲訊號輸入至時域對數位碼轉換器來輸出數位碼,後六位元則使用傳統Vcm-Based之連續漸進式類比數位轉換器產生。此混合型連續漸進式類比數位轉換器減少了電容切換的次數以及比較器的使用次數,相比於傳統的連續漸進式類比數位轉換器能有效地減少功率消耗以及節省切換時間進而達到高速取樣頻率以及低功耗的需求。製程方面使用TSMC 65nm來設計,模擬輸入訊號頻率為0.44MHz時,訊號對雜訊諧波比為57.15dB,有效位元數9.201bits,平均功率消耗則為3.513mW。
Abstract(英文摘要)
With the rapid development of technology, the transmission of information on the accuracy and speed requirements are more demanding for the mobile communication system, that the design of high-speed circuit architecture seems to have become a trend in contemporary society.
Signal in nature are all continuous analog signals, but it is common to process data in digital signals, so between the analog and digital signals, we need an analog-to-digital converter to convert both signals, and the successive approximation register analog-to-digital converter is more widely used, this analog-to-digital converter without additional operation amplifier circuit architecture, relative to other analog-to-digital converter, it occupies less circuit area and has low power consumption advantage.
This thesis implements a 150ms/s 10bits hybrid SAR ADC with time-domain analysis, the first four bits was generated by time domain analysis analog-to-digital converter, and the last six bits use traditional Vcm-based successive approximation register analog-to-digital converter to generate. This hybrid analog-to-digital converter reduce the number of switching times on capacitor and the compare times to comparator, that it can reduce power consumption effectively and save the switching time to achieve high-speed sampling frequency and low power consumption. The proposed ADC design in TSMC 65nm process, when input signal frequency is 0.44MHz, the signal to noise and distortion ratio is 57.15dB, the effective number of bits is 9.201bits, and the average power consumption is 3.513mW.
參考文獻
[1] G.Y. Huang, C.C. Liu, Y.-Z. Lin, and S.J. Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," in IEEE ASSCC Dig. Tech. Papers, pp. 157-160, November 2009.
[2] J. Craninckx and G. Plas, “A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-sharing SAR ADC in 90nm Digital CMOS,” IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247.
[3] W. Liu, P. Huang, and Y. Chiu, “A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC Achieving Over 90dB SFDR,” IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 380-381
[4] Shuo-Wei Michael Chen et al, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13 μm CMOS” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2669-2680, DECEMBER 2006
[5] C.C. Liu, et al, ‘‘A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,’’ IEEE J. Solid-State Circuits, vol.45, no. 4, Apr. 2010, pp. 731-740.
[6] B.P.Ginsburg and A.P.Chandrakasan ‘‘An energy-efficient charge recyclingapproach for a SAR converter with capacitive DAC, ’’ Proc. IEEE Symp. Circuits Syst., pp.184 -187 2005
[7] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration,” IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384-385.
[8] R. Kapusta et al., “A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3059–3066, Dec. 2013.
[9] S. Haenzsche, S. Henker, and R. Schuffny, “Modelling of Capacitor Mismatch and Non-Linearity Effects in Charge Redistribution SAR ADCs,” in Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Jun. 2010, pp. 300-305.
[10] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol 45, no. 4, pp. 731-740, Apr. 2010.
[11] W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou, and C. K. Wang, “A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications,” IEEE A-SSCC Dig. Tech. Papers, Nov. 2009, pp. 149-152
[12] Yan Huang, H.Schleifer, and D.Killat, “Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs” Circuit Theory and Design (ECCTD), Sept. 2013
[13] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.
[14] Goran Jovanović, Mile Stojčev, Dragiš Krstić: “Delay Locked Loop with Linear Delay Element”, in Proc. of 7-th International Conference TELSIKS, vol. 2, pp. 397-400.
[15] Dudeck P. et al., “A high–resolution CMOS time–to–digital converter utilizing a vernier delay line”, IEEE Journal of Solid–State Circuits, vol. 35, No. 2, pp. 240–246, February 2000
[16] G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, Facta Universitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp. 215-232, August 2003.
[17] G. S. Jovanović and M. K. Stojčev: “Current starved delay element with symmetric load”, International Journal of Electronics, pp. 167- 175, Vol. 93, No 3, March 2006.
[18] J. P. Janson et al., “A CMOS time-to-digital converter with better than 10ps single-shot precision,” IEEE J. Solid-State Circuits, Vol. 41, No. 6, pp. 1286-1296, June, 2006.
[19] M. Lee and Asad A, Abidi, “A 9b, 1.25ps resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue,” IEEE J. Solid-State Circuits, Vol. 43, No. 4, pp. 769-777, Apr., 2008.
[20] M. H. Chung, H. P. Chou, "A Time-to-Digital Converter Using Vernier Delay Line with Time Amplification Technique", Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 23-29 Oct. 2011, Hsinchu, Taiwan, pp. 772-775
[21] V. H. Bui, Seunghyun Beak, Seunghwan Choi, Jongkook Seon and T. T. Jeong, "Thermometer-to-binary encoder with bubble error correction (BEC) circuit for Flash Analog-to-Digital Converter (FADC)," Communications and Electronics (ICCE), 2010 Third International Conference on, Nha Trang, 2010, pp. 102-106.
[22] C. Lin and M. Syrzycki, "Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution,"Circuits and Systems, Vol. 2 No. 4, 2011, pp. 365-371.
[23] M. Moazedi, A. Abrishamifar and A. M. Sodagar, "A highly-linear modified pseudo-differential current starved delay element with wide tuning range," 2011 19th Iranian Conference on Electrical Engineering, Tehran, Iran, 2011, pp. 1-4.
[24] Gang Luo and Xianjun Zeng, "An improved voltage-controlled delay line for delay locked loops," Computer Research and Development (ICCRD), 2011 3rd International Conference on, Shanghai, 2011, pp. 237-240.
[25] B. Razavi, Design of Analog CMOS Integrated Circuit. Boston, MA: McGraw-Hill, 2001.