此篇論文分成兩個部份，分別為雷射二極體驅動電路設計以及低電壓差動訊號電路設計與量測，在每個部份皆會詳細說明電路設計的流程並用直觀的方式說明所需瞭解之電路運作原理。
雷射二極體驅動電路設計包含利用電路模擬軟體完成整體雷射二極體驅動電路之設計與佈局以及如何模擬光纖模組。由於光訊號在經過光纖時會因色散等效應而造成碼際干擾，會影響訊號讀出的正確性。而此雷射二極體驅動電路採用多水管的架構將碼際干擾消除，以確保電路在高頻操作時依然能讀出正確的訊號。並將設計時所需瞭解之電路運作原理在時域上表示，同時將雷射二極體驅動電路在佈局需特別注意高頻操作時的匹配和走線等詳細說明。
低電壓差動訊號設計考量到單位時間內可以傳輸大量資料，並達到低抖動和共模特性、訊號完整性。此篇設計為改良磁滯接收器之輸出緩衝閘和設計量測時之高速印刷電路板，以達到量測時可接收到高速且正確的資料。
此低電壓差動訊號晶片使用0.18微米製程，操作在1.8伏特時搭配設計的高速印刷電路板量測時可達到500Mbps的良好眼圖，並符合低電壓差動訊號傳輸介面的規格。此晶片含有4個通道，4個通道的差異在於輸出緩衝閘的不同，但量測時皆可達到500Mbps的眼圖，同時證實了此晶片的重現性與可靠度。

This thesis includes two parts, namely the laser diode driver circuit design and low-voltage differential signal circuit design and measurement, both of them will be described in detail in each part of the design flow and illustrated the principle of operation by intuition.
Laser diode driver circuit design includes the use of circuit simulation software and layout of the whole laser diode driver circuit. Also how to simulate the fiber modules. The light signals pass through the optical fiber because of chromatic dispersion and other effects caused by the ISI, which will affect the accuracy of the signal read out. This laser diode driver uses the taps architecture to cancel the ISI effect to ensure that the data can be read out correctly at high frequency. The principle of the circuits operation will be illustrated in the time domain. The laser diode drive circuit layout has few critical points need to know at high frequency operation, suck as matching and alignment, etc. Those key points illustrate in detail.
LVDS circuit design considers the large amounts of data that can be transmitted per unit of time and achieves low jitter, common mode characteristic and signal integrity. This part design of modified hysteresis receiver and buffer, while the measurement can receive fast and correct data.
This LVDS chip using 0.18 micron process and operating at 1.8 volts with the design of high-speed PCB can reach 500Mbps of eye diagram, and comply the specifications of LVDS. This chip contains four channels, which difference with the buffer, all of the channels can achieve 500Mbps eye diagram at measurement. It confirms the reproducibility and the reliability of this chip.

[1] "IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)," in IEEE Std 1596.3-1996
[2] "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, "ANSI/TIA/EIA-644-1995, Telecommunications Industry Association, Nov.15, 1995.
[3] Y. Unekawa, K. Seki-Fukuda, K. Sakaue, T. Nakao, S. Yoshioka, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motoyama, Y. Ohba, K. Ise, M. Ono, K. Fujiwara, Y. Miyazawa, T. Kuroda, Y. Kamatani, T. Sakurai, A. Kanuma, "A 5 Gb/s 8/spl times/8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200 MHz LVDS interface," Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC, 1996 IEEE International, San Francisco, CA, USA, 1996, pp. 118-119.
[4] P. Xiao, D. Kuchta, K. Stawiasz, H. Ainspan, Joong-Ho Choi and Hyun Shin, "A 500 Mb/s, 20-channel CMOS laser diode array driver for a parallel optical bus," Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International, San Francisco, CA, USA, 1997, pp. 250-251.
[5] A. Boni, A. Pierazzi and D. Vecchi, "LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr 2001.
[6] Y. Lin, W. Kang, X. Chen, J. Zhang, X. Zou, "A novel 1.2 Gbps LVDS receiver for multi-channel applications," Proceedings of the 2009 12th International Symposium on Integrated Circuits, Singapore, 2009, pp. 287-290.
[7] G. Mandal and P. Mandal, "Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface," 2005 IEEE International Symposium on Circuits and Systems, 2005, pp. 2180-2183 Vol. 3.
[8] M. d. Ker, C. h. Wu, "Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications," 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 5155-5158.
[9] B. Young, "An SOI CMOS LVDS driver and receiver pair," VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on, Kyoto, Japan, 2001, pp. 153-154.
[10] C. y. Chen, J. h. Wang and T. p. Sun, "A Novel Mini-LVDS Receiver in 0.35-um CMOS," 2006 IEEE International SOC Conference, Taipei, 2006, pp. 65-68.
[11] S. Palermo and M. Horowitz, "High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects," 2006 Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, 2006, pp. 508-511.
[12] K. Szczerba, P. Westbergh, J. Karout, J. S. Gustavsson, Å. Haglund, M. Karlsson, P. A. Andrekson, E. Agrell, A. Larsson, "4-PAM for high-speed short-range optical communications," in IEEE/OSA Journal of Optical Communications and Networking, vol. 4, no. 11, pp. 885-894, Nov. 2012.
[13] J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov, H. A. Ainspan, B. D. Parker, M. P. Beakes, A. Chung, T. J. Beukema, P. K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, D. J. Friedman, "A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006.
[14] H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, B. J. Tom, M. Fiorentino, M. Hochberg, S. Palermo, P. Y. Chiang, "22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS," 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3.
[15] R. A. Philpott, J. S. Humble, R. A. Kertis, K. E. Fritz, B. K. Gilbert and E. S. Daniel, "A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS," 2008 IEEE Custom Integrated Circuits Conference, San Jose, CA, 2008, pp. 623-626.
[16] T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker, M. Beakes, "A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization," in IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.
[17] R. Farjad-Rad, Chih-Kong Ken Yang, M. Horowitz and T. Lee, "A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver," VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on, Kyoto, Japan, 1999, pp. 41-44.
[18] J. Bulzacchelli, T. Beukema, D. Storaska, P. H. Hsieh, S. Rylov, D. Furrer, D. Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, R. Kelkar, H. Ainspan, W. Kelly, G. Ritter, J. Garlett, R. Callan, T. Toifl, D. Friedman, "A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology," 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2012, pp. 324-326.
[19] P. C. Chiang, J. Y. Jiang, H. W. Hung, C. Y. Wu, G. S. Chen and J. Lee, "4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 573-585, Feb. 2015.
[20] Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O, Optical Internetworking Forum, Sep. 2011 [Online]. Available: http://www.oiforum.com/public/documents/OIF_CEI_03.0.pdf
[21] J. Y. Jiang, P. C. Chiang, H. W. Hung, C. L. Lin, T. Yoon and J. Lee, "100Gb/s ethernet chipsets in 65nm CMOS technology," 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, 2013, pp. 120-121.
[22] A. Maxim, "Notice of Violation of IEEE Publication Principles
A 3.3 V 12.5 Gb/s 0.2 m SiGe BiCMOS Laser Diode Driver Using Bias Current Modulation Cancellation," in IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2086-2098, Oct. 2007.
[23] N. Chujo, T. Takai, T. Sugawara, Y. Matsuoka, D. Kawamura, K. Adachi, T. Kawamata, T. Ohno, K. Ohhata, "A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 9, pp. 2061-2068, Sept. 2011.