研究生: |
莊旻倫 Min-Lun Chuang |
---|---|
論文名稱: |
可逆序列元件之合成 Synthesis of Reversible Sequential Elements |
指導教授: |
王俊堯
Chun-Yao Wang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 英文 |
論文頁數: | 29 |
中文關鍵詞: | 可逆邏輯合成 |
外文關鍵詞: | reversible logic synthesis |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在建立可逆序列電路時,我們必須使用到可逆序列元素。所以,如何設計可逆序列元素是個非常重要的問題。本篇論文提出一些可逆元素的新設計架構,如:D型閂鎖器,JK型閂鎖器,以及T型閂鎖器。依據這些不同型式的可逆閂鎖器,我們可以設計出相對應的可逆正反器。接下來,我們更進一步的討論使用我們所設計的可逆序列元素,對於可逆序列電路測設成本的影響。與前人所提出的可逆序列元素設計相比較,我們設計的可逆序列元素所需要的製造成本(包含了所需邏輯閘的個數以及無用的輸出訊號個數)都低了許多。
To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as the D latch, JK latch, and T latch. Based on these reversible latches, we construct the designs of the corresponding flip-flops. Then, we further discuss the test costs, including the test generation and test application, of reversible sequential circuits with these reversible flip-flops. Compared with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs is considerably reduced.
[1] C. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, 17: pp. 525-532, Nov. 1973.
[2] E. Fredkin and T. Toffoli, “Conservative logic,” International Journal of Theoretical Physics, vol. 21, pp. 219-253, 1982.
[3] E. Knill, R. Laflamme, and G. J. Milburn, “A scheme for efficient quantum computation with linear optics,” Nature, pp. 46-52, Jan. 2001.
[4] P.Kerntopf, “A new heuristic algorithm for reversible logic synthesis,” in Proc. of the IEEE Design Automation Conference, pp. 834-837, 2004.
[5] R. Landauer, “Irreversibility and heat generation in the computational process,” IBM Journal of Research and Development, 5: pp. 183-191, July 1961.
[6] R. C. Merkle, ”Two types of mechanical reversible logic,” Nanotechnology, 4:pp. 114-131, 1993.
[7] D. Maslov and G. W. Dueck, ”Garbage in reversible design of multiple output functions,” in Proc. of 6th International Symposium on Representations and Methodology of Future Computing Technologies, pp. 162-170, 2003.
[8] D. M. Miller, “Spectral and two-place decomposition techniques in reversible logic,” in Proc. of the IEEE Midwest Symposium on Circuits and Systems (MWCAS), pp. II493–II496, 2002.
[9] D. M. Miller, D. Maslov, and G. W. Dueck, “A transformation based algorithm for reversible logic synthesis,” in Proc. of the IEEE Design Automation Conference, pp. 318-323, 2003.
[10] M. M. Mano, “Computer engineering: hardware design,” Prentice-Hall, Englewood Cliffs, NJ, 1988.
[11] R. C . Merkle, and K. Drexler, “Helical Logic,” Nanotechnology, 7: pp.325-339, 1996.
[12] M. Nielsen and I. Chuang, “Quantum computation and quantum information,” Cambridge University Press, 2000.
[13] M. Perkowski, L. Joziwak, A. Mixhchenko, A. Al-rabadi, A. Coppola, A. Buller, X. Song, M. Khan, S. Yanushkevich, V. P. Shmerko, and M. Chrzanowska-Jeske, “A general decomposition for reversible logic,” in Proc. of Reed-Muller Workshop, pp. 119-138, 2001.
[14] K. N. Patel, J.P. Hayes, and I.L. Markov, ”Fault testing for reversible circuits,” in Proc. of the IEEE VLSI Test Symposium, pp. 410-416, 2003.
[15] P. Picton, “Multi-Valued Sequential Logic Design using Fredkin Gates,” Multiple-Valued Logic Journal, vol.1, pp. 241-251, 1996.
[16] J.P. Hayes, I. Polian and B. Becker,” Testing for Missing-Gate Faults in Reversible Circuits,” in Proc. of the IEEE Asian Test Symposium, pp.100-105, 2004.
[17] J. E. Rice,” A New Look at Reversible Memory Elements", in Proc. of the IEEE International Symposium on Circuits and Systems, 2006.
[18] G. Schrom, ”Ultra-low-power CMOS technology,” PhD thesis, Technischen Universitat Wien, June 1998.
[19] H. Thapliyal and M. B. Srinivas, “A beginning in the reversible logic synthesis of sequential circuits,” in Proc. of Military and Aerospace Programmable Logic Devices International Conference, 2005.
[20] T. Toffoli, “Reversible computing,” Tech memo MIT/LCS/TM-151, MIT Lab for Comp. Sci, 1980.
[21] A. De Vos and Y. Van Rentergem, “Reversible computing: from mathematical group theory to electronical circuit experiment,” in Proc. of the 2nd conference on Computing Frontiers, 2005.
[22] T. W. Williams and R. Mercer, “Design for Testability – A survey,” IEEE Transaction on Computers, C 31, pp. 2-15, 1982.
[23] M. J. Y. Williams and J. B. Angell, ”Enhancing Testability of Large-Scale Itegrated Circuits via Test Points and Additional Logic,” IEEE Transaction on Computers, C22, pp.46-60, 1973.
[24] G. Yang, X. Song, W. N.N. Hung, and M. A. Perkowski, “Fast Synthesis of Exact Minimal Reversible Circuits using Group Theory,” in Proc. of the IEEE Asia and South Pacific Design Automation Conference, pp. 1002-1005, 2005.
[25] V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. I. Bourianoff, “Limits to Binary Logic Switch Scaling–A Gedanken Model,” in Proc. of the IEEE, pp. 1934-1939, 2003.