研究生: |
劉冠麟 Liu, Kuan Lin |
---|---|
論文名稱: |
應用於多光譜遙測衛星之時間延遲多次積分線性掃描互補式金氧半導體影像感測器 A Time Delay Multiple Integration Linear CMOS Image Sensor for Multispectral Satellite Telemetry |
指導教授: |
謝志成
Hsieh, Chih Cheng |
口試委員: |
鄭國興
邱進峯 鄭桂忠 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 英文 |
論文頁數: | 83 |
中文關鍵詞: | 時間延遲積分 、互補式金氧半導體影像感測器 |
外文關鍵詞: | Time Delay Integration, CMOS Image Sensor |
相關次數: | 點閱:2 下載:0 |
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本論文提出一個應用於多光譜(Multispectral)衛星遙測之線性互補式金氧半導體影像感測器,利用時間延遲多次積分(Time Delay Multiple Integration)技術提高影像的訊雜比(Signal-to-Noise Ratio)。
為了得到高電荷轉電壓增益,本論文採用Y型轉Δ型(Y-to-Delta)金屬-氧化物-金屬(Metal-Oxide-Metal)電容結構為積分電容之電容反饋跨阻抗放大器(Capacitive Trans-impedance Amplifier)作為像素架構。利用本論文所提出之類比與數位累積的混合架構,所實作之時間延遲多次積分器配合加法器與靜態隨機存取記憶體(Static Random-Access Memory)庫,將時間延遲積分(Time Delay Integration)、多次取樣(Multiple Sampling)、以及類比數位轉換等功能整合在單一晶片上。利用兩組記憶體庫,數位式相關雙採樣(Digital Correlated Double Sampling)也完成實現在此實作中。
為了驗證本電路,一個8級、128行的時間延遲積分線性互補式金氧半導體影像感測器原型使用0.18微米1P6M標準互補式金氧半導體製程製作,晶片總面積為2500×5200 μm2。在8級時間延遲積分、以及每次時間延遲積分中多次取樣64次的操作下,量測結果顯示在線時間為414.72微秒的操作時間下,感光靈敏度為40.42 V/lux∙s,訊雜比提升約為9.37dB,在1.8伏特的操作電壓下,系統功耗為17.77毫瓦。
This thesis presents a linear CMOS image sensor for multispectral (XS) satellite telemetry with time delay multiple integration (TDMI) technique to improve the signal-to-noise ratio (SNR) of imaging.
To achieve high conversion gain, the capacitive trans-impedance amplifier (CTIA) based pixel with Y-to-Delta (Y-Δ) metal-oxide-metal (MOM) capacitor network as the integration capacitor is adopted in this work. With the proposed hybrid structure of analog and digital accumulation, the implemented time delay multiple integrator, cooperating with the adder and static random-access memory (SRAM) bank, integrates the functions of time delay integration (TDI), multiple sampling (MS), and analog-to-digital conversion in a single chip. By using two memory bank, the digital correlated double sampling (D-CDS) has also been implemented in this work.
An 8-stage 128-column TDMI linear CMOS image sensor prototype was fabricated in 0.18-μm 1P6M standard CMOS technology with a chip area of 2500×5200 μm2. With an operation of 8 stages TDI and 64 times MS per TDI stage, the measurement result shows that the sensitivity is 40.42 V/lux∙s at a line time of 414.72 μs, the resulting SNR improvement is 9.37 dB, and operating at 1.8 V supply voltage, the power consumption is 17.77 mW.
[1] US patent 3971065, Bryce E. Bayer, "Color imaging array", issued 1976-07-20
[2] G. Lepage, D. Dantès, and W. Diels, “CMOS long linear array for space application,” in Proc. Electron. Imag. Conf., Jan. 2006, vol. 6068, pp. 61–68.
[3] G. Lepage, J. Bogaerts, G. Meynants, “Time-Delay-Integration Architectures in CMOS Image Sensors,” IEEE Trans. Electron Devices, Nov. 2009, vol. 56, pp. 2524-2533.
[4] J. Ohta, Smart CMOS Image Sensors and Applications, CRC Press
[5] B. Fowler, J. Balicki, D. How and M. Godfrey, “Low-FPN high-gain capacitive transimpedance amplifier for low-noise CMOS image sensors,” Proc. SPIE vol. 4306, p. 68, May. 2001.
[6] Y. Lim, "A 1.1e- temporal noise1/3.2-inch 8 Mpixel CMOS image sensor using pseudo-multiple sampling", IEEE ISSCC Dig. Tech. Papers, pp. 396-397, 2010
[7] Fu-Kai Tsai, Hong-Yi Huang, Li-Kuo Dai, Cheng-Der Chiang, Ping-Kuo Weng, Yung-Chung Chin, “A time-delay-integration CMOS readout circuit for IR scanning,” in Proc. 9th Int. Conf. Electron., Circuits Syst., 2002, vol. 1, pp. 347-350
[8] Y. Nitta et al., “High-speed digital double sampling with analog CDS on column parallel ADC architecture for low-noise active pixel sensor,” in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, Feb. 2006, pp. 2024–2031
[9] K. Yonemoto, “Fundamentals and Applications of CCD/CMOS Image Sensors,” Q Pub. Co., Ltd., Tokyo Japan, 2003. In Japan.
[10] Cheng,Sheng-Coung, "Trade-off Study on Fill Factor of Self-Reliant CMOS FPA", Doc No: ITRC-RSFS5.RSIMEMO-00-980807, (2009)
[11] Hui Tian, Boyd Fowler, and Abbas El Gamal, “Analysis of Temporal Noise in CMOS Photodiode Active Pixel Sensor,” IEEE JSSC, vol.36, no.1, pp. 92-101, Jan. 2001
[12] Tom Henderson, Circular Motion and Satellite Motion, The Physics Classroom
[13] National Space Organization, National Applied Research Laboratories
http://www.nspo.org.tw/tw/
[14] C. B. Kim C. H. Hwang, B. H. Kim, Y. S. Lee, H. C. Lee, “CMOS TDI readout circuit that improves SNR for satellite IR applications,” Electronic Letters, 2008, vol.44, pp.346-347
[15] K. Nie, S. Yao, J. Xu, J. Gao, and Y. Xia, “Thirty Two-stage CMOS TDI Image Sensor With On-Chip Analog Accumulator,” IEEE Trans. On VLSI Systems, vol.22, no.4, pp.951-956, April 2014
[16] K. W. Cheng, C. Yin, C. C. Hsieh, W. H. Chang, H. H. Tsai, and C.F. Chiu, “Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor,” International Symposium on VLSI-DAT, pp.1-4,2012
[17] J. H. Chang, K. W. Chen, C. C. Hsieh, W. H. Chang, H. H. Tsai, and C. F. Chiu, “Linear CMOS image sensor with time-delay integration and interlaced super resolution pixel,” in Proc. IEEE Sensors, pp.1-4, Oct.2012
[18] H. Michaelis, R. Jaumann, S. Mottala, J. Oberst, R. Kramm, R. Roll, H. Boehnhardt, H. Michalik, and G. Neukum, “CMOS-APS sensor with TDI for high resolution planetary remote sensing,” in Proc. IEEE CCD AIS Workshop, 2005, pp. 31–34.
[19] K. Nie, S. Yao, J. Xu, J. Gao, and Y. Xia, “A 128-stage analog accumulator for CMOS TDI image sensor,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 7, pp. 1952–1961, Jul. 2014.
[20] E. R. Fossum and D. B. Hondongwa, “A review of pinned photodiode for CCD and CMOS image sensors,” IEEE J. Electron Devices Soc., vol. 2, no. 3, pp. 33–43, May 2014.
[21] James R. Janesick, Photon Transfer DN to [lambda], SPIE Press, 2007
[22] R. Xu, B. Liu, and J. Yuan, “A 1500-fps highly sensitive 256x256 CMOS imaging sensor with in-pixel calibration,” IEEE J. Solid-State Circuits, vol. 6, no. 6, pp. 1408–1418, Jun. 2012.
[23] P. Rombouts, W. De Wilde, and L. Weyten, “A 13.5-b 1.2-V micropower extended counting A/D converter,” IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 176–183, Feb. 2001.
[24] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato and A. Baschirotto “Behavioral modeling of switched-capacitor sigma delta modulators”, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 3, pp.352 -364 2003
[25] Yamei Li and Lili He, “First-Order Continuous-Time Sigma-Delta Modulator,” Quality Electronic Design, 2007. ISQED '07. 8th International Symposium
[26] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000
[27] M. W. Seo, S. H. Suh, T. Iida, T. Takasawa, K. Isobe, T. Watanabe, K. Isobe, T. Watanabe, S. Itoh, K. Yasutomi, and S. Kawahito, “A low noise high intrascene dynamic range CMOS image sensor with a 13 to 19b variable-resolution column-parallel folding-integration/cyclic ADC,” IEEE J. Solid-State Circuits, vol. 47, pp. 272–283, 2012
[28] M. van Elzakker, et al., “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge- Redistribution ADC,” ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2008.
[29] M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall 1979, 0-13-214510-3 pp. 119–123.
[30] S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis & Design, McGraw Hill, 1995, Chapter 2.
[31] Eiichiro Oda, ONE PIECE WEB: http://www.j-onepiece.com/
https://zh.wikipedia.org/zh-tw/ONE_PIECE#/media/File:ONE_PIECE_Logo.svg