流量控制機制主要目的為：晶片網路系統中緩衝器的資源分配。發送授權流控制機制(credit-based flow control)被廣泛的使用在目前的系統上。支援推測模式的發送授權流量控制機制主要的做法是基於原來的機制上修改，以達到與原始機制相輔相成的功效。本實驗主要的目的是Verilog硬體敘述語言(HDL)建立一個支援推測模式(speculation mode)的發送授權流量控制機制的模型。將此模型與擁有4個連接埠，並且具有緩衝器的縱橫式網路架構(crosspoint network)結合，用來驗證整個流量控制機制的正確性，並且移植至元件可编程邏輯閘陣列(FPGA)，用以驗證硬體層(hardware level)次的功能正確性。
效能分析方面，我們同樣的以Verilog硬體敘述語言建構一個支援推測是流量控制機制且可連結16個核心的網狀網路(mesh network)，並且調整緩衝器的大小、連線造成的延遲、或是可接受推測的封包數，調整這些硬體參數以分析硬體條件對於流量控制機制所產生的效能影響。除此之外我們還建構了兩種封包流動模型，以分析不同的封包流動趨勢對網路效能造成的影響。

Flow control mechanism controls buffer usage for packet transmitting from node to node. Speculative flow control has been proposed in [2]. First, we design and implement this flow control mechanism by Verilog HDL. We build up a buffered crosspoint network with speculative flow control in RTL for functional correctness and then implement the crosspoint network model into FPGA for real hardware simulation.
We also discuss the influence of speculative flow control on performance. We build up a 4x4 mesh network models with credit-based flow control and speculative flow control by Verilog HDL in RTL level. We tune some parameters of the network model, such as buffer size, delay time between adjacent nodes and speculated packet size for evaluation. We also build up two types of traffic model for the mesh network to show the influence of traffic on the network. Hardware cost in FPGA and ASIC is also presented.

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