渦輪碼已經是近年來通道編碼理論的一項重大突破。渦輪碼的低功率設計對現今的通訊系統來說是一個相當重要的研究課題。而在渦輪解碼裡軟式輸入軟式輸出解碼演算法中，以最大事後機率演算法最強而有力。然而，最大事後機率演算法解碼器在硬體實現上需要大量的記憶體，因此，在渦輪碼的架構中，用來儲存分支路徑值以及狀態路徑值的記憶體，不論在功率的消耗或是在面積上都佔了整個架構的大部分。因此在本論文中是以儲存編碼端的輸入值以及時計算產生分支路徑值而不是儲存計算出的分支路徑值。本論文還採用一種創新的最大事後機率解碼器架構，藉由儲存邊界路徑值簡化後向反覆運算，同時節省分支路徑值儲存數量。另外，提出一個簡化儲存狀態路徑值記憶體的方法，根據渦輪碼時間對應計算排程圖的分析，前向反覆運算可以直接地被轉換與後向反覆運算同時同向處理，此方法只需增加少量的額外硬體架構便可，並可以有效地減少記憶體單元與面積。從比較結果中，更可看出此方法比起以往的研究更有效地減少到一半的記憶體存儲數量。除此之外，提出的架構不像以往的研究，此方法簡化了記憶資料存取的動作，而不需要其他額外的位址產生器。最後經由實驗結果顯示在我們提出的方法在錯誤率分析的結果上幾乎沒有差異，而在面積及功率消耗的比較上分別節省了約一半以上。

In coding theory, turbo codes have been the breakthrough in recent years. Among these, the maximum a posteriori (MAP) probability algorithm is a powerful soft-input soft-output (SISO) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This thesis presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Besides it adopted the concept of the border metrics to reduce the memory size and the power consumption of the memory accesses. Based on the scheduling analysis, the forward recursion can be reversed in order to be directly operated on with backward recursion. The comparison result shows it can effectively reduce the memory size up to more than half size of the previous works. In addition, we also simplify the memory data access without an extra address generator.

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