雷達按照發射信號種類分成脈衝雷達和連續波雷達兩大類，常規脈衝雷達發射周期性的高頻脈衝，連續波雷達發射的是連續波信號。連續波雷達發射的信號可以是單頻連續波(CW)或者調頻連續波(FMCW)，調頻方式也有多種，常見的有三角波、鋸齒波、編碼調製或者噪聲調頻等。其中，單頻連續波雷達僅可用於測速，無法測距，而FMCW雷達既可測距又可測速，並且在近距離測量上的優勢日益明顯。
而要有一展頻連續波的訊號，需要一個能產生展頻訊號的鎖相迴路，來提供FMCW雷達所需的展頻功能，在本論文中即提出一個操作在6.2 GHz ~ 7 GHz可展頻之具有三角積分調變器的數位式鎖相迴路，主要組成的電路有相位頻率檢測器、電流幫浦、三階迴路濾波器、壓控振盪器、除頻器、三角積分調變器以及能使鎖相迴路產生展頻訊號的三角波產生器。在設計上除了利用運算放大器降低電流幫浦的非理想效應，並將電流幫浦做成電流可調的能力，透過調整電流改變迴路頻寬，使輸出訊號具有最好的雜訊壓抑，並且在不使用展頻時，十六位元的三角積分調變器能提供相當高的解析度，上述中的子電路構造出完整的鎖相迴路架構。
本文開頭介紹動機，並對後續章節做簡單介紹，接著講解鎖相迴路中子電路的架構，在說明在本論文中所使用的論文架構，並提出電路之模擬結果，最後對提出的鎖相迴路做簡單的結論。

According to the type of transmission signal, radar is divided into two types, pulse radar and the continuous wave radar, normally pulse radar emits periodic high-frequency pulse and continuous wave radar emits a continuous wave signal. The signal transmitted by the CW radar may be a single- frequency continuous wave (CW) or a frequency-modulated continuous wave (FMCW), and there are also various frequency modulation methods, such as triangular wave, saw tooth wave, code modulation, or noise frequency modulation. Among them, single-frequency continuous-wave radar can only be used for speed measurement, while FMCW radar can not only measure distance but also speed.
To have a continuous-wave signal with spread-spectrum, a spread-spectrum signal is required to provide by phase-locked loop for the FMCW radar. In this paper, a 6.2 ~ 7 GHz Spread-Spectrum Phase-Locked Loop w/i Delta-Sigma Modulator is proposed. The main circuit are phase frequency detector, charge pump, 3rd loop filter, voltage-controlled oscillator, frequency divider, and delta-sigma modulators, and a triangular wave generator circuit which make the PLL generating a spread-spectrum signal, using operating amplifier to reduce the non-ideal effect of the charge pump, and make the charge pump have the function of current-adjustable, to have the best noise suppression in output signal, and when the spread spectrum is not used, the 16-bit delta-sigma modulator can provide a very high resolution of frequency, the above sub-circuits construct a complete phase-locked loop architecture.
This thesis begins with an introduction to the motivation, and gives a brief introduction to the following chapters, the behavior of phase-locked loop and the design flow were described step-by-step. And a brief conclusion for the PLL in the last chapter.

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