近幾年，三五族高銦含量的砷化銦鎵通道高電子遷移率電晶體(High Electron Mobility Transistors，HEMTs)在高速度及低耗能邏輯應用方面展現出極大潛力，本研究中成功製作高速與低功率應用之高效能砷化銦通道高電子遷移率電晶體，並運用了先進的製程技術大幅提升了砷化銦通道高電子遷移率電晶體元件邏輯特性。
　　本論文中利用銦含量百分之百的砷化銦作為通道層材料成長於晶格匹配的磷化銦基板，並運用了電極板技術、非合金歐姆接觸技術、二次閘極蝕刻以及白金閘極掘入技術成功的製作出九十奈米閘極線寬的砷化銦高電子遷移率電晶體，利用這些技術使元件展現優異的邏輯特性。此研究比較了在低操作偏壓下(VDS=0.5V)電極板結構與平面結構電晶體之間的電性差異。
　　發現透過了電極板製程步驟改善了元件的電場分佈，使元件展現出非常高的崩潰電壓8.3伏特和相當低的次臨界擺幅 64.1mV/decade，此外，其開關電流比值達到 2.4×104，以及非常小的汲極能障降低 44mV/V，由這個研究結果可以證實，電極板技術能大幅改善邏輯元件特性，因此極具潛力作為下個世代的高速邏輯電晶體應用。

In the recent years, high indium content InGaAs-based HEMTs have high potential for high-speed and low-power logic application. 90 nm gate length InAs-channel high electron mobility transistors (HEMTs) have then been fabricated with success and characterized for high-frequency and low-power logic applications. The logical performance of the InAs-channel HEMTs was improved by using advance techniques.
　　In this thesis, the indium content is used and one hundred percent of the InAs-channel were grown on lattice match In-P substrates. The 90 nm InAs HEMTs processed with field plate techniques, Ti/Pt/Au non-alloyed ohmic process, two-step recess and Pt gate sinking technologies for logic applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 90 nm InAs HEMTs with these advanced processes perform better than the traditional InAs HEMTs at low applied voltage, for example: better current saturation, lower output conductance (go), lower negative threshold-voltage (VT) , smaller subthreshold swing (SS). The excellent electronic performances indicate that the developed 90 nm InAs HEMTs are suitable for high-speed and low voltage applications.
　　In this thesis, the fabrication of 90 nm InAs-channel HEMTs using field plate was developed. We have demonstrated that the field plate technique can realign the electrical field distribution to improve device performance. The devices show great performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 44 mV/V, subthreshold swing (SS) is 64.1 mV/decade, ION/IOFF ratio achieved 2.4 × 104, and much higher breakdown voltage achieved 8.3 V. These results show that the field plate technologies substantially improve logic device performance. Therefore, it has great potential for high-speed and low-power logic application for the next generation.

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