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研究生: 鄭家豐
Chia-Feng Chen
論文名稱: 具有光感測器的液晶顯示面板的二位元輸出讀取電路
A binary readout circuit for photo detector equipped LCD panel
指導教授: 黃惠良
Huey-Liang Hwang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 產業研發碩士積體電路設計專班
Industrial Technology R&D Master Program on IC Design
論文出版年: 2006
畢業學年度: 95
語文別: 英文
論文頁數: 66
中文關鍵詞: 比較器液晶顯示面板光感測器輸出讀取電路
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  • 近年來,平板顯視觸控輸入應用領域,利用非晶矽薄膜電晶體當作光感側元件的應用及發展越來越多元化。於配合主動式液晶顯示器的應用上,通常需要外部多加元件,此如電阻式、電容式 或是電感式的觸控平板元件。這不僅增加元件的材料成本,也相對的影響顯示器的光穿透效率。但若是搭配內建於顯示器的被動式感應電路來使用,則可省去外部多加元件,並可大幅提昇透光度及解析度。此設計為利用平面顯示器前段製程技術,將光感側元件製作在每一個影像畫素中,利用相同於驅動液晶的非晶矽薄膜電晶體,來當感測光信號的元件。此時每一個光信號將可透過光感測電晶體而儲存下來,再經由循序的電路定址,輸出所要的信號,即可達到讀取的功能。
    本篇論文裡介紹一種應用在感光式液晶顯示面板的輸出讀取電路,由於感光式的面板是利用光二極體當感應器並且利用光筆當輸入所以容易受背景光源的干擾,本篇論文的重點在於利用雙重取樣的方式和切換電容電路做訊號相減來減少雜訊干擾以及提高訊雜比,並利用遲滯型比較器來作類比數位的訊號轉換,優點在於可以縮小電路面積並避免訊號因雜訊干擾而跳動產生的訊號誤判,並且可以利用調整參考電壓與電流的方式對比較器的操作電壓範圍作調整,以及對遲滯電壓的範圍控制,來達到高增益低雜訊且小面積的電路特性,藉由這樣的讀出電路我們可以對應輸入訊號的軌跡,將輸入的光訊號做正確的讀出。本篇論文的模擬參數是採用 TSMC0352P4M 製程,以HSPICE為模擬軟體。


    Recently, for interactive purposes, detecting devices are been developed on the existing TFT-LCD panels. Many of them are based on resistive, capacitive or inductive touch technology. All these solutions require externally added components or one more layer of screen, which add the cost and degrade the optical performance. In our study, we use a novel approach by building an additional TFT photo-diode in the existing LCD display pixel as a detecting element. This diode can be embedded during the panel manufacturing process and incurring no additional cost. After the post-product evaluation, this diode also shows no impediment to the light efficiency. In this way, by using the photo-diode array and by going with a designed detecting circuit, the imaging signal that appears on the panel can then be read out.
    In this study we investigate a binary read out circuit that can be used to distinguish an ON/OFF signal that comes from a light beam spot shone on a photo detector array equipped in a LCD panel. In this structure, because the back light source can cause error during the signal read out period, here we used the correlated double sample (CDS) method to reduce the noise. By this way we can trace the moving light spot locus on the panel and transfer the coordinate data to the following processor for further processing. Besides, we used the hysteresis comparator as an analog to binary signal converter. This comparator circuit has designed with a bistable characteristic that has an adjustable threshold, so that the other noise influence such as thermal noise and dark current that comes from the LCD panel can be minimized. The parameters that influence the threshold variations and loop of hysteresis are observed. The circuit proposed above is design in a TSMC 0.35um process and verified by HSPICE program.

    LIST OF CONTENTS ABSTRACT ……………………………………………………………1 ACKNOELEDGRMENT……………………………………………………3 LIST OF CONTENTS………………………………………………… 4 LIST OF FIGURES……………………………………………………6 LIST OF TABLES…………………………………………………… 9 CHAPTER 1: Introduction of TFT photo sensor array10 1-1 Introduction………………………………………………… 10 1-2 Flat- panel Imager using a-Si TFT Array………………12 1-3 Fingerprint Scanner Using a-Si : H TFT Array……… 14 1-4 TFT Arrays for Direct-Conversion X-Ray Sensors and High-Aperture AMLCDS……………………………………………………18 1-5 Active Matrix LCD with Integrated Optical Touch Panel-Planar system………………………………………………………21 CHAPTER 2: Noise and the readout circuit………………… 25 2-1 Introduction of the noise…………………………………25 2-1-1 Thermal noise………………………………………………25 2-1-2 Dark current……………………………………………… 26 2-1-3 Fixed pattern noise………………………………………26 2-2 Noise reduction method…………………………………… 27 2-3 Comparator…………………………………………………… 38 2-3-1 Comparator using hysteresis……………………………38 CHAPTER 3: Architectures of the readout circuit…………40 3-1 Introduction of the readout circuit……………………40 3-2 Correlated double sampling circuit…………………… 42 3-3 Switched-Capacitor circuit……………………………… 44 3-4 Hysteresis comparator………………………………………………………… 47 CHAPTER 4: Simulation result………………………………… 50 4-1 CDS simulation……………………………………………… 50 4-2 Switched-capacitor circuit simulation…………………56 4-3 Hysteresis comparator simulation……………………… 60 CHAPTER 5: Conclusions………………………………………… 63 REFERENCES………………………………………………………… 64

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