本論文描述一個10位元二階迴圈式類比數位轉換器。並就類比數位轉換器中最重要的取樣與保值電路，以及殘值處理產生器做非線性誤差的分析，分析結果可以得到電路的開關大小對於非線性誤差有很大的影響，開關過大準確性降低，過小則速度不夠，所以必須取到最佳值，另外相位邊限必須大於60度才能避免震盪現象。類比數位轉換器模擬結果顯示其訊號雜訊比為59.099dB，微分非線性度為0.5LSB，積分非線性度為0.7LSB。由於運算放大器與開關及電容的匹配度是限制精確度的最主要因素，加入一個具有6位元slider的Sliding Scale補償電路，可以有效降低DNL，由於Sliding Scale是利用工作點分散平均法來降低微分非線性度，所以通道取樣數的多寡也會直接影響到補償效果的好壞，另外slider的數量也是另一個決定補償效果的因素，但就另一觀點來說，slider的數量越多會使得可使用的通道數目減少，可視系統需求來決定。在補償電路的模擬方面分別使用3位元及6位元的slider，所得到的微分非線性度分別為0.125LSB及0.053LSB，總括來說Sliding Scale的確可以有效降低微分非線性度，只要補償電路的誤差可以降到最低。

1. P. Vorenkamp and J. P. M. Verdaasdonk, “A 10 b 50 MS/s pipelined ADC”, Digest of Technical Papers, 39th IEEE International Solid-State Circuits Conference (ISSCC), pp. 32-33, 1992
2. T. B. Cho and P. R. Gray, “ A 10-bit, 20-MS/s, 35Mw pipeline A/D converter”, Proceedings of the IEEE Custom Integrated Circuit Conference, pp. 499-502
3. J. S. Xie “Nyquist-Rate A/D Converter Design” Chip Implementation Center 2003
4. J. T. Wu, “Analog Integrated Circuit,” NCTU Xin-zhu Taiwan R.O.C. 2002
5. A. Kitagawa, M. Kokubo, T. Tsukada, T. Tsukada, and T. Imaizumi, “A 10b 3Msample/s CMOS Cyclic ADC.” Int. Solid State Circuit Conf. (ISSCC), pp. 280-281 (Feb. 1995)
6. Y. M. Lin, B. Kim and P. R. Gray “A 13-b 2.5MHz Self-Calibrated Pipelined A/D Converter in 3-um CMOS”, IEEE, JSSC, Vol. 26 pp. 628-636 (April 1991)
7. S. H. Lewis, “Optimizing the stage resolution in pipelined, analog-to-digital converters for video-rate applications”, IEEE Transactions on Analog and digital Signal Processing Circuit and Systems II, Vol. 39, No. 8, pp. 516-523, August 1992
8. I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 318-325, March 2000
9. C. Cottini, E. Gatti and V. Svelto, “A new Method for analog to digital conversion,” Nucl. Instr. And Meth, 24 241-242. (1963)
10. A. C. Dent and C. F. N. Cowan, “Linearization of analog-to-digital converters,” IEEE Transactions on Circuits and Systems, Vol. CAS-37, pp.729-737. (Jun. 1990)
11. 鄭尚元 “核儀類比數位轉換器微分非線性度補償技術之研究” NTHU 1992碩士論文
12. B. Razavi “Design of Analog CMOS Integrated Circuits” McGraw-Hill Companies Inc. 2001
13. M. J. McNutt , S. LeMarquis, and J. L. Dunkley,” Systematic Capacitance Matching Errors and Corrective Layout Procedures”, IEEE Journal o Solid-State Circuits, Vol. 29, No. 5, (May 1994)
14. D. Sayed and M. Dessouky , “Automatic Generation of Common- Centroid Capacitor Arrayswith Arbitrary Capacitor Ratio”, IEEE Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition.
15. 黃善君“10位元10MHz導管式類比數位轉換器數位校正方法之研製” NTU 2001 碩士論文
16. D. A. Johns and K. Martin “Analog Integrated Circuit Design,” John Wiley & Sons, Inc., 1997
17. R. Gregorian ”Introduction to CMOS OP-amps and Comparators” John Wiley & Sons.,1999
18. L. Sumanen, M. Walyari, and K.A.I.Halonen, ”A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,”in Proc.ICECS, vol.1, pp.32-35 (Dec.2000)
19. Daniel D. Gajski, “Principles of Digital Design,” Prentice-Hall, Inc 1996
20. R. Ockey and M. Syrzycki, “Optimization of a latched comparator for high-speed analog-to-digital converter”, IEEE Canadian Conference on Electrical and Computer Engineering, Vol. 1, pp. 403-408, 1999
21. E.G. Soenen and R.L. Geiger, “Analog and Digital Signal Processing,” IEEE Transactions on Circuits and Systems II, Vol. 42 Issue: 3 , pp. 143 –153 (March 1995)
22. D. W. Cline and P. R. Gray, “A power optimized 13-b 5 Ms/s pipelined ADC“ IEEE Journal of Solid-State Circuits, Vol. 31 Issue: 3, pp. 294 –303 (March 1996)
23. A. M. Abo and P. R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 34, NO.5, (May 1999)
24. Y. M. Lin, “Performance limitations on high-resolution video rate analog digital interfaces,” Memo. No. UCB/ERL M90/55, 19 (June 1990)
25. 20﹒C. Y. Wu; S. Y. Chin and S. S. Chang “A new capacitor- ratio - independent algorithmic analog-to-digital converter”, IEEE International Symposium on Circuits and Systems, vol.3 pp. 2228 -2231 (1990)
26. H. T. Yung and K. S. Chao, “A ratio-independent cyclic A/D conversion technique”, IEEE International Symposium on Circuits and Systems, pp. 2581 -2584 vol.3 (1988)
27. M. Gustavsson, J. J. Wikner and N. Nick Tan” CMOS Data Convertor For Communications” Kluwer Academic Publishers, 2000
28. M. M. Mano “Digital Design” Prentice-Hall, Inc.,1991
29. C. C. Enz, G. C. Temes, ”Circuit techniques for reducing the effects of op-amp imperfections: auto zeroing, correlated double sampling, and chopper stabilization” Proceedings of the IEEE, Vol. 84 Issue 11, pp. 1584 –1614 (Nov. 1996)