本論文提出一個創新的低功率消耗混合式數位至類比轉換器：半二元權重式與半接觸分裂式數位至類比轉換器，適用於10位元的生醫訊號擷取的連續漸進式類比至數位轉換器，並將操作電壓設計在0.9V，類比電路操作在次臨界區，以追求更低的功率消耗。
為了減少不同段落的數位至類比轉換器間存在的不同的增益誤差所造成的電壓偏差，本論文也在不同的數位至類比轉換器上加上假的比較器以抵銷不同增益誤差所造成的偏差電壓。
比較器的kick-back noise在此架構也產生比其他架構更大的影響，因此本論文也將傳統的rail-to-rail比較器進行修改以降低kick-back noise對前面數位至類比轉換器的影響。
在pre-simulation可得到1.27μW的功率消耗，訊號對雜訊與總諧波比為61.7dB，換算為有效位元數為9.96-bit，價值指標為12.8 fJ/conversion step。
晶片的設計實現採用了tsmc 0.18μm 1P6M CMOS製程，晶片佈局面積為893�e893μm2，扣掉pad的核心電路面積為440�e430μm2。在post-layout模擬結果可以得到1.72μW的功率消耗，訊號對雜訊與總諧波比為59.1dB，換算為有效位元數為9.53-bit，價值指標為23.2 fJ/conversion step。
在0.9V的供應電壓，取樣頻率為100KS/s下進行量測實驗，可以得到1.59μW的功率消耗，訊號對雜訊與總諧波比為46.47dB，換算為有效位元數為7.43-bit，價值指標為92.2 fJ/conversion step。晶片最低可在0.6V的供應電壓下操作，消耗功率僅為0.783μW。
量測結果雖在訊號對雜訊與總諧波比項目較不理想，本論文也在第六章結論部分進行討論與分析，並提出相對應的改善方法。

This thesis proposes a novel 0.9V 10-bit Successive Approximation (SAR) analog-to-digital converter (ADC) based on half junction splitting (J.S.) and half binary weighted capacitor digital-to-analog converter (DAC) architecture. The kick-back noise of this structure due to comparator is larger than other DAC structures, thus a modified rail-to-rail comparator is used to reduce kick-back noise. This ADC is implemented in sub-threshold to reduce power consumption. In addition, dummy comparators are used in different sections of DAC to reduce the offset voltage caused by different gain errors of different DAC sections. The pre-simulation shows that the power dissipation is 1.27μW, SNDR is 61.7dB, ENOB is 9.96-bit, and figure-of-merit (FOM) is 12.8 fJ/conversion step.
The chip has been fabricated with TMSC 0.18μm 1P6M CMOS process. The chip area is 893�e893μm2 with pads, and the core area is 440�e430μm2. The post-layout simulation shows that the power consumption is 1.72μW, the SNDR is 59.1dB, ENOB is 9.53-bit, and FOM is 23.2 fJ/conversion step.
Under 0.9V supply voltage and 100KS/s sampling rate, the measurement result shows that the power dissipation was 1.59μW, SNDR was 46.47dB, ENOB was 7.43-bit, and FOM was 92.2 fJ/conversion step. This chip worked under 0.6 V supply voltage and consumed only 0.783μW. This low-power ADC is suitable for bio-medical signal acquisition.
This low-power ADC is suitable for bio-medical signal acquisition.

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