由於近年的科技快速進步，有高偵測率的光偵測器在生活中的應用日漸增加，但如何創造出操作電壓小、耗能小以及易於外部電路整合成單一晶片等優點的單光子偵測器並沒有獲得足夠的研究。而普遍常見的單光子崩潰二極體的操作電壓大約在十幾伏特以上，為了使操作電壓可以更少，本論文將嘗試設計單光子崩潰電晶體(SPAT)當作光偵測器使用。
本篇論文的橫向光電晶體架構皆為不更動任何現有製程條件的情況下，利用TSMC 0.18μm 標準CMOS製程製作，且在其MOSFET結構下利用寄生的電晶體設計低崩潰電壓之光偵測器。利用電晶體的BVCBO>BVCEO特性，使電晶體操作電壓定為BVCEO，且嘗試利用元件的Base和MOSFET結構特有的Gate外接出冷卻電路。
然而量測結果發現，因為MOSFET中橫向寄生BJT結構上先天的問題，造成電場過於集中在BC接面轉角處，在逆向偏壓達到估計可發生崩潰之數值時，雖然轉角處電場及Impact Generation Rate 夠大，但Base 與Collector接面平面處之電場卻過小，而無法全面發生累增崩潰，導致在偵測光子時無法達到預期產生SPAT脈衝計數之效果。

Along with the rapid improvement of technology, the applications of photodetectors with high sensitivity increase gradually. However, creating single photon avalanche detector with low bias voltage, low power consumption and easy integration with quenching circuit, did not drawn research effort. Generally, Single Photon Avalanche Diode (SPAD) is biased at high voltage larger than 12V. This work, in order to reduce operation voltage, attempts to design a Single Photon Avalanche Transistor(SPAT) as a photodetector.
In this work, a SPAT with low breakdown voltage is presented in TSMC 0.18μm standard CMOS process without any process modifications. The SPAT is a lateral parasitic transistor (LPT) in a MOSFET structure. The SPAT is biased at BVCEO by taking advantage of the characteristic of a transistor, BVCBO>BVCEO. Besides, we try to design a quenching circuit based on the Base and the Gate in a MOSFET structure.
Measurement shows that because the structure of LPT in MOSFET is born with some problems, electric field is concentrated at the corner of BC junction. Although reverse bias is large enough to make avalanche breakdown happen at the corner of BC junction, the impact generation at the large planar region of the BC junction is still not large enough to contribute to avalanche breakdown. Therefore, the I-V curve is not steep and pulse counts cannot be observed in the SPAT as hoped.

[1] M. Kalverkamp, J. B. Hauge, and K. Thoben, "Logistics IoT services development with a sensor toolkit in an experiential training environment," in 2013 International Conference on Engineering, Technology and Innovation (ICE) & IEEE International Technology Management Conference, 24-26 June 2013 2013, pp. 1-8, doi: 10.1109/ITMC.2013.7352666.
[2] 戴嘉邑，“標準CMOS製程之單光子偵測器”，國立交通大學，電子工程研究所，碩士論文，中華民國九十九年八月
[3] S. Radovanovic, A.-J. Annema, and B. Nauta, High-speed photodiodes in standard CMOS technology. Springer Science & Business Media, 2006.
[4] S. O. Kasap, “Photodetectors and Image Sensors,” Optoelectronics and Photonics : Principles and Practices,2nd ed. New Jersey, Pearson, 2012, ch5, sec.4, pp378-379.
[5] H. T. Yen, “ InGaAs Avalanche Photodiode for Single-Photon-Detector Application”, Master thesis, National Chiao Tung University, Taiwan, 2012.
[6] R. Henderson, G.-F. Dalla-Betta, L. Pancheri, D. Stoppa, and J. Richardson, "Avalanche photodiodes in submicron CMOS technologies for high-sensitivity imaging," Advances in Photodiodes, 2011.
[7] B. F. Aull et al., "Geiger-mode avalanche photodiodes for three-dimensional imaging," Lincoln Laboratory Journal, vol. 13, no. 2, pp. 335-349, 2002.
[8] S. M. Sze and K. K. Ng, Physics of semiconductor devices. John wiley & sons, 2006.
[9] A. Gallivanoni, I. Rech, and M. Ghioni, "Progress in Quenching Circuits for Single Photon Avalanche Diodes," IEEE Transactions on Nuclear Science, vol. 57, no. 6, pp. 3815-3826, 2010, doi: 10.1109/TNS.2010.2074213.
[10] C. Niclass, M. Gersbach, R. Henderson, L. Grant, and E. Charbon, "A Single Photon Avalanche Diode Implemented in 130-nm CMOS Technology," IEEE Journal of Selected Topics in Quantum Electronics, vol. 13, no. 4, pp. 863-869, 2007, doi: 10.1109/JSTQE.2007.903854.
[11] A. G. Stewart, L. Wall, and J. C. Jackson, "Properties of silicon photon counting detectors and silicon photomultipliers," Journal of Modern Optics, vol. 56, no. 2-3, pp. 240-252, 2009/01/20 2009, doi: 10.1080/09500340802474425.
[12] F. d. S. Campos, N. Faramarzpour, O. Marinov, M. J. Deen, and J. W. Swart, "Photodetection With Gate-Controlled Lateral BJTs From Standard CMOS Technology," IEEE Sensors Journal, vol. 13, no. 5, pp. 1554-1563, 2013, doi: 10.1109/JSEN.2012.2235827.
[13] 林祐玄，“標準CMOS製程下實現高響應度橫向光感測器電晶體之研究＂，國立清華大學，電子工程研究所, 碩士論文, 中華民國一百零六年十月
[14] 姜毅，“一個具有Body-strapped Base的雙極光電晶體反應速度之方法＂，國立清華大學，電子工程研究所, 碩士論文, 中華民國一百零七年八月
[15] L. Cheung Fai and P. K. T. Mok, "A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique," IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 3-14, 2004, doi: 10.1109/JSSC.2003.820870.
[16] J. Han and M. Meyyappan, "Trigger and Self-Latch Mechanisms of n-p-n Bistable Resistor," IEEE Electron Device Letters, vol. 35, no. 3, pp. 387-389, 2014, doi: 10.1109/LED.2013.2297277.
[17] 沈昇鴻, “標準SiGe BiCMOS製程中實現高響應度及高速光偵測電晶體＂, 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零四年七月