MOS元件為目前半導體工業的主要驅動力，但隨著MOS元件的縮小化，許多原本在長通道MOS元件中較不重要的參數已慢慢浮現出來。因此，有相當多的研究報告都在討論如何使MOS元件在通道長度愈來愈短的情況下，依然可以保持長通道時的良好特性。其中，MOS元件的寄生電阻更是不可忽視之課題， 這是由於它不如預期般的隨著MOS元件的縮小化而縮小。因此擁有一個有效的MOS元件寄生電阻模型來正確地預測和分析源極/汲極寄生電阻在未來的MOS元件中是必要的。

在本論文中，我們先瞭解了長通道(Paresitic Resistance Model of Long Channel MOSFET)和短通道寄生電阻模型(Paresitic Resistance Model of Short Channel MOSFET)的優缺點後，接著提出了改良後短通道寄生電阻模型(Improved Parasitic Resistance Model of Short Channel MOSFET)。此改良後短通道寄生電阻模型經過元件模擬軟體(MEDICI)的驗證，發現確實可以改善原本短通道寄生電阻模型在閘極電壓較小的情況下，短通道寄生電阻模型嚴重低估源極/汲極寄生電阻的缺點。因此，我們所提出的改良後短通道寄生電阻模型能更有效的預測MOS元件寄生電阻。並且在我們模擬的過程中，我們也對MOS元件源極/汲極寄生電阻的各項特性加以模擬分析，希望能明確的看出MOS元件的其他結構參數(Overlap、SDE Junction Depth、Spacer、Abruptness、Halo等)對MOS元件源極/汲極寄生電阻之影響。並且也探討這些結構參數對MOS元件源極/汲極寄生電阻的物理意義和原因，以致於能更有效的降低未來MOS元件的源極/汲極寄生電阻，提高MOS元件的可靠度和性能。

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