為了滿足低功率和高效率的需求，現今設計支援多功率模式及匯流排亂序交易，然而，也造成了時序錯誤、軟錯誤和死結問題。為了有效率的容錯及避免這些問題，我們提出了閘層級和計算機結構層級的最佳化方法。
第一部分，針對多功率模式的設計，我們提出了閘層級時序最佳化的方法。我們使用可調式延遲緩衝器建立一個可調式時脈樹，使得可以在不同功率模式之下指定有用的時脈偏移。我們使用線性規劃指定了不同功率模式之下的可調式延遲緩衝器的延遲，我們也提出了一個加速理論加速線性規劃的速度，最後，我們提出了一個有效率的方法選擇可調式延遲緩衝器的位置。
第二部分，我們提出了一個雙層級的軟錯誤容錯方法論，為不同應用妥協效率、功率和可靠性。我們提出了四種不同容錯能力的正反器設計，接著，我們提出雙層級的易受傷度分析，可以找出容易受到程式錯誤影響的正反器，最後，我們提出一個最佳化流程去擺放這些有容錯能力正反器的位置。
第三部分，針對匯流排亂序交易的設計，我們提出了計算機結構層級的死結避免機制。我們提供新穎的辨識號碼指定方法並且保證不會發生死結，更靈活的規則也被提出用以指定辨識號碼，借此大幅度的降低匯流排的暫停狀況。

To satisfy low-power and high-performance requirements, modern designs support advanced features such as multi-power modes and out-of-order transactions. However, these features may lead to occurrences of timing errors, soft errors, and deadlocks. To efficiently tolerate or avoid the occurrences of these errors and deadlocks, we propose several gate-level and architecture-level optimization methods.
First, we propose a gate-level timing optimization for multi-power mode designs. We use Adjustable Delay Buffers (ADBs) to construct a tunable clock tree so that useful skew can be assigned for different power modes. Then, we assign the delays of the ADBs for each power mode by Linear Programming (LP). A speedup theorem is proposed to greatly reduce the inequalities for the LP. We also propose an efficient heuristic to select the positions of ADBs.
Second, we present a dual-level soft-error tolerant design methodology to trade off performance, power, and reliability for different applications. Four novel detection and correction Flip-Flop (FF) structures are proposed to provide different levels of tolerance capability against soft errors. Then, architecture-level vulnerability analysis and gate-level susceptibility analysis are employed to identify weak FFs that can easily cause program execution errors. An optimization framework is developed to synthesize the proposed four novel FF structures into weak and highly-observable storage bits.
Third, we develop architecture-level deadlock-free mechanisms for the designs supporting out-of-order transactions. We provide a novel ID assignment mechanism which guarantees the issued transactions to be deadlock-free. Flexible rules are also presented for the ID assignment problem to greatly reduce the number of transaction stalls.

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