為了迎接物聯網所產生的大數據時代之來臨，雲端計算將會需要硬體方面能處理大量的資料傳輸、搜尋以及比對。
三元內容循址記憶體提供了在一個計時器周期內比對整個二維陣列資料的能力。這種高速的性質造就了三元內容循址記憶體被廣泛應用在網路路由器和比較表。 然而傳統以靜態隨機存取記憶體為基底的三元內容循址記憶體將會面臨到兩大問題: 較大的記憶體單元面積以及較高的功耗。傳統的三元內容循址記憶體由16顆電晶體構成，其中以兩個六電晶體的靜態隨機存取記憶體和四電晶體組成的比較電路構成。這種16顆電晶體的結構造成過大的面積而提高了製造成本。另一方面，由於平行搜尋的特性，三元內容循址記憶體產生的大量的功耗，這會造成過低的搜尋效率以及過高的功耗密度。這個問題在先進製程下將會日趨嚴重。三大造成高功耗的部分分別為: 比對線、搜尋線以及記憶單元的漏電流，這三者占了搜尋功耗的一大部分。 而在三項之中，配對線佔據了最大量的比例。兩種降低配對線功耗最直觀的方法為: 用較低的電壓對配對線充電或是降低其上的電容。以前的設計通常採用第一種的方法。至於記憶單元的漏電流部分，降低記憶單元的電壓源可以有效的達到目的，然而這個方法將會在傳統操作上降低配對線放電速度或是在充電式操作上造成較小的電壓差異。
總而言之，三元內容循址記憶體的設計上會遇到兩大問題為降低記憶單元面積以及功耗。在本次設計中，我們提出一種全新的14電晶體架構之記憶單元，此記憶單元將可以達到: (1) 相較於傳統設計有較小的單元面積 (2) 相較於傳統設計，配對線上有較小的負載而達到較低的功耗。
由於這種新型的架構，其寫入以及搜尋的操作將會異於傳統。寫入部分不像傳統的雙邊寫入，我們採用單邊寫入並用直行方向的資料感應式記憶單元壓降搭配字元線升壓來幫助寫入的動作。
本次晶片是透過二十八奈米製程技術搭配修改之後的緊密6電晶體靜態隨機存取記憶體構成一容量為三十二萬字元之14電晶體三元內容循址記憶體，藉由此新型架構以及操作技巧，本研究可達到
1. 相較於傳統記憶單元，本作為0.9倍之記憶單元面積。
2. 搜尋時間可達到0.9奈秒。
3. 能量效率為0.546 fJ/search/bit。在標準化之後，在二八奈米或是更先進之技術
中為最好的。

With the coming of the era of Big Data caused by Internet-of-Things (IoT), cloud computing requires hardware with the ability to data transmission, searching and comparing.
Ternary Content Addressable Memory (TCAM) provides the ability to compare input search data against an array of stored information in a single clock cycle. This high-speed property makes TCAM widely used in network routers and look-up tables. However, the conventional SRAM-based TCAM suffer from two main issues: larger bit cell area and high power. For a conventional TCAM, it is composed of 16 transistors including two 6T-SRAM bit cells and 4T-comparison logic. This 16T bit cell structure results in large area in TCAM array causing high cost. On the other hand, because the fully parallel search operation, TCAM produces large amount of power consumption, and leads to poor search efficiency and high power density. This problem will go more severe in advanced process. The three most power consuming parts in TCAM are: match-line (ML), search-line (SL) and bit cell leakage, they account for very great proportion of power consumption during searching. Among these three, ML consumes most power. The two direct methods to reduce ML power is to apply lower voltage to charge ML or reduce capacitance on ML. The previous works usually adopt the former. As for the bit cell leakage, reducing cell-VDD (CVDD) could efficiently decrease the leakage power. However, this method causes lower speed in traditional ML developing scheme or poor margin sensing margin in current racing scheme.
Overall, the two big challenges to overcome in TCAM design is to reduce bit cell area and power consumption. In this work, we propose a brand new 14T TCAM bit cell to achieve following goals: (1) Smaller area than conventional 16T SRAM-based TCAM bit cell; (2) Less loading on ML to reduce power consumption of ML;
Because the new structure of proposed cell, the write and search operation are different from conventional 16T-TCAM. Unlike conventional differential writing, 14T-TCAM adopt single-ended write and use column-wise data aware cell-VDD (CVDD) down scheme with word-line (WL) boost to assist the write margin.
A 1024x288b 14T-TCAM macro is fabricated using 28nm process with modified foundry compact-cell 6T cell, which can achieve:
1. 0.9 times area smaller than traditional 16T SRAM-based TCAM.
2. 0.9ns search time.
3. 0.546 fJ/search/bit Energy efficiency, which is the best in 28nm or advanced technology after normalization.

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