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研究生: 林鉅翊
Lin, Chu-Yi
論文名稱: 適用於3GPP之高基數渦輪解碼器
High Radix Turbo Decoder for 3GPP
指導教授: 黃元豪
Huang, Yuan-Hao
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 94
中文關鍵詞: 渦輪解碼器渦輪碼最大事後機率最大事後機率 解碼器高基數通道編解碼
外文關鍵詞: turbo decoder, turbo code, MAP, MAP decoder, high radix, channel coding
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  • 在第三代行動通訊(3rd Generation Partnership Project,3GPP)中,渦輪碼被使用在資料的編碼上,因為資料的傳輸需要較好的錯誤更正能力。在下一代系統中,隨著渦輪解碼器(turbo decoder)的使用率增加,使得最大事後機率(Maximum A-Posteriori,MAP)解碼器的解碼速度也越來越重要。因此,此論文的重心在設計一個高吞吐量(high throughput)的渦輪解碼器中的最大事後機率解碼器。我們提出一個radix-16最大事後機率演算法來降低解碼週期和一個補償項(modify term)的方法來改善解碼的性能。然後,我們又提出一個分離式比較選擇器(separate-Comparator Selector,separate-CS)架構可以同時處理十六個輸入來降低運算時間和一個用於交錯器(interleaver)記憶體的切段跳序排列(cut-bank-jump-permute)法來解決大部分的記憶體相撞(memory collision)問題。最後,我們將其解碼器做成晶片。此解碼器的吞吐量為393Mb/s且優於部分參考文獻結果。此外,我們提出來的解碼器還可以結合其他技術在同樣的性能上將吞吐量更加的提高。


    For the 3rd Generation Partnership Project(3GPP) specification, the turbo code is applied
    in the transmitted data because the data needs a better error correction capability.
    With the increase of the utilization of the turbo decoder in the next generation system,
    decoding speed for the MAP decoder has become more and more critical. Hence, the
    target of this thesis is to design a high throughput MAP decoder for the turbo decoder.
    We propose a radix-16 MAP algorithm to reduce the decoding cycle, and a modified
    term method to improve the decoding performance. Then, we propose a separate-CS
    architecture which can operate sixteen inputs simultaneously to reduce the latency of
    the MAP decoder, and a cut-bank-jump-permute method for the interleaver memory
    to solve the collision problem. Finally, we implement the proposed high-radix modified
    log-MAP decoder. The throughput of the proposed decoder is 393Mb/s which is better
    than some references. Moreover, the proposed decoder can combine the other techniques
    even to increase the throughput in the same performance.

    1 Introduction 1.1 Research Motivation 1.2 Organization of This Thesis 2 Turbo Code 2.1 Introduction 2.2 Turbo Encoder 2.2.1 Convolutional Encoder 2.2.2 Recursive Systematic Convolutional Encoder 2.2.3 Trellis Termination for Turbo Encoder 2.2.4 State Transition Diagram 2.2.5 Internal Interleaver 2.3 Turbo Decoder 2.3.1 Log Likelihood Ratios (LLR) 2.3.2 Maximum A-Posteriori (MAP) Algorithm 2.3.3 Max-Log-MAP Algorithm 2.3.4 Modified Log-MAP Algorithm 2.3.5 Iterative Turbo Decoding 2.4 Sliding Window 2.5 Several Improving Throughput Techniques 3 Proposed High Radix Modified Log-MAP Algorithm 3.1 High Radix MAP Algorithm 3.1.1 Radix-16 State Metrics 3.1.2 Radix-16 Branch Metrics 3.1.3 Radix-16 LLR 3.2 High Radix Modify Term Method 3.2.1 Full Modification 3.2.2 Top-Term Modification 3.2.3 Bottom-Term Modification 3.2.4 Proposed Effectively Modify Term 4 Proposed High Radix Turbo Decoder Architecture 4.1 Turbo Decoder Architecture 4.2 MAP Decoder Architecture 4.2.1 Branch Metrics Calculator 4.2.2 Memory Selection 4.2.3 State Metrics Calculator 4.2.4 LLR Calculator 4.3 Proposed Comparator-Selector Architecture 4.3.1 Power CS Architecture 4.3.2 Location CS Architecture 4.3.3 Separate CS Architecture 4.3.4 Movable Separate CS Architecture 4.3.5 Characteristic for Proposed CS Architecture 4.4 Interleaver 4.4.1 Collision Problem 4.4.2 Collision Reduction 5 Radix-16 Modified Log-MAP Decoder Implementation 5.1 Time Schedule Diagram 5.1.1 Time Schedule for Branch Memory 5.1.2 Time Schedule for Calculation Processer 5.1.3 FSM for Main Controller 5.2 Chip Layout and Specification 5.3 RTL Simulation 5.4 Throughput Comparison 5.5 Proposed CS Synthesis Comparison 6 Conclusion

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