符合進階高速匯流排規格的低功率、高效能之JPEG2000區塊編碼架構

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研究生：	謝天威 Tien-Wei Hsieh
論文名稱：	符合進階高速匯流排規格的低功率、高效能之JPEG2000區塊編碼架構 A Low Power and High Performance AHB-compliant EBCOT Architecture for JPEG2000 Encoding
指導教授：	林永隆 Youn-Long Lin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	36
中文關鍵詞：	JPEG2000影像壓縮標準、區塊編碼、內容產生器、算術編碼器
外文關鍵詞：	JPEG2000, EBCOT, Context Formation, Arithmetic Encoder
相關次數：	點閱：3 下載：0
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我們在這篇論文中提出一個低功率、高效能的區塊編碼(Embedded Block Coding with Optimized Truncation)架構，用以加速JPEG2000影像壓縮。區塊編碼分為兩個步驟：內容產生(Context Formation)和算術編碼(Arithmetic Encoder)。在內容產生方面，我們提出十六位元平行處理架構，用以減少計算所花的時脈週期以達低功率消耗。在算術編碼方面，我們提出三級管線化的架構，可以提升整個區塊編碼的輸出能力。我們另外設計符合進階高速匯流排(Advanced High-performance Bus)規格的介面，讓我們的區塊編碼器可以整合到以進階微控制器匯流排架構(Advanced Microcontroller Bus Architecture)為基礎的單晶片系統(Silicon on a Chip)上。最後，我們與現在最好的設計做比較，我們的設計可以再節省17%的計算週期；若以內容產生的個數做為下限，我們的設計只比最佳解多5%的計算週期。

We propose a low power and high performance Tier-1 architecture of Embedded Block Coding with Optimized Truncation (EBCOT) in the JPEG2000 encoder. In the context formation, we use a parallel structure for low power consumption, a memory-saving algorithm to decrease memory access, a memory arrangement to utilize bandwidth efficiently, and a stripe-skipping method for performance benefit. In the arithmetic encoder, we adopt a modified probability estimation table and a forwarding method to implement pipelined architecture. We present a renormalization strategy that can save cycles during the coding process. Our design is easily integrated into the AMBA-based system as an accelerator. Compared with the best-known column-based method, we reduce the cycle count by 17%. Let the number of context-decision (CX, D) pairs be the lower bound on the cycle count, we have achieved 5% within the optimum.

Contents
ABSTRACT..................................................I
CONTENTS.................................................II
LIST OF FIGURES .........................................IV
LIST OF TABLES ...........................................V
CHAPTER 1 ................................................1
INTRODUCTION..............................................1
CHAPTER 2.................................................5
RELATED WORK .............................................5
 2.1 TIER-1 CODING ALGORITHM............................. 5
  2.1.1 Context Formation ................................7
  2.1.2 Arithmetic Encoder ..............................10
 2.2 PREVIOUS DESIGNS .................................. 11
  2.2.1 Normal Mode .....................................11
  2.2.2 Pass-Parallel Mode...............................12
 2.3 COMPARISON......................................... 13
CHAPTER 3................................................15
PROPOSED ARCHITECTURE ...................................15
 3.1 TIER-1 ENCODER .................................... 15
 3.2 CONTEXT FORMATION.................................. 16
 3.3 ARITHMETIC ENCODER................................. 20
CHAPTER 4................................................24
IMPLEMENTATION ..........................................24
 4.1 IP DESIGN FLOW .................................... 24
 4.2 IP INTERFACE ...................................... 25
CHAPTER 5................................................28
EXPERIMENTAL RESULTS.....................................28
 5.1 DESIGN REPORTS..................................... 28
 5.2 EXPERIMENTAL RESULTS............................... 29
CHAPTER 6................................................32
CONCLUSIONS .............................................32
BIBLIOGRAPHY.............................................33

                                

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