我們利用我們現有的矽智財以及系統研發方法在一個多媒體的單晶片平台上面提出了一個 H.264/AVC主要規範編碼器。
在這個編碼器中我們使用了一個可以根據畫面類型彈性調整流水線操作階層數量的架構。我們使用了一個改良過後的模式決策器使我們的編碼器可以達到與參考軟體近乎相同畫質。我們使用了四個特別的記憶體存取裝置來處理我們對於編碼器外面記憶體的存取，並且在存取裝置中使用了一種預先讀取的機制來加強我們的效能。在畫面之間的影像預測，我們使用了一個可以減少記憶體存取次數的機制，來減少所需要的頻寬。同時我們使用了一種在矽智財間直接連結的架構來加強我們的效能。我們同時提出了我們在平台上所需要軟體的工作流程圖，以及介紹我們的編碼器如何與系統的架構溝通。
在完成之後我們的編碼器可以在我們的實驗平台上以每秒三十張畫面的速度下即時編碼 352 x 288畫素大小的影像。利用上述所提出的特性，我們的編碼器在平台下的工作頻率為18百萬赫茲並且可以燒入一個六百萬邏輯閘大小的現場可程式化邏輯閘陣列。與參考軟體相比較，我們的編碼器在速度上有約三百三十倍以上的提昇。

We propose an H.264/AVC main profile encoder based on our in-house IP-level and system-level degign methodology targeted towards a multimedia SOC platform. We employ a flexible four-stage pipelined architecture to enhance the performance. We use a modified mode decision cost formula which can achieve almost the same video quality as that of the reference software. We use multiple memory fetch units to access external memory. For inter prediction, we employ a memory reuse mechanism to reduce memory traffic. We also use direct connection between certain IP to boost the performance. After implementation, our design can real-time encode the video of 352x288 pixels with 30 fps into an H.264 main profile video stream on our platform. With the proposed special mechanisms, our design only needs to run at 18 MHz and can be burned into a 6M gate count FPGA. Comparing with the performance of the reference software, our is 300 times faster with only a little video quality tradeoff.

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