60V橫向汲極雙擴散電晶體之設計｜國立清華大學博碩士論文庫

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研究生：	陳立凡 Chen, Li-Fan
論文名稱：	60V橫向汲極雙擴散電晶體之設計 The Design of 60V Double Diffuses Drain Metal Oxide Semiconductor Field Effect Transistor Device
指導教授：	龔正 Gong, Jeng 黃智方 Huang, Chin-Fang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 半導體元件及製程產業研發碩士專班 Industrial Technology R&D Master Program on Semiconductor Devices and Manufacturing Process
論文出版年：	2010
畢業學年度：	98
語文別：	中文
論文頁數：	52
中文關鍵詞：	汲極雙擴散、金氧半場效電晶體
相關次數：	點閱：1 下載：0
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In recent years, designing a low power consumption, high breakdown, and high speed device is a significant topic for discussion. In order to integrate power devices with planar IC process, the devices structure must be changed from the traditional vertical structure to lateral design, such that they can integrated in the same chip. In this thesis we use the simulation software of process and electricity to analyze the influence of different size of structure of the DDDMOS devices from simulation are chosen to be realized by the chance of actual tapeout. Furthermore, the simulation also utilize NBL to design High-side device. Finally, the results of actual device structures measurement and electrical analysis show that the DDDMOS device structures which can achieve the purpose of design.

近年來，設計一個低功耗，高崩潰電壓和高速元件是一個重要的議題。功率元件為了與平面製程整合，必須將傳統垂直式的元件結構改成橫向式設計因而可與低壓電路整合於同一晶片上在本論文中利用製程與電性的影響進而設計不同結構的DDDMOS並從所選取之元件作為下線的結構。接者，從NBL模擬實驗中實現了High-side條件並從實際元件結構量測，最後得到符合預期設計的結果。

Abstract....................................................................................................i
摘要.........................................................................................................ii
致謝........................................................................................................iii
目錄.........................................................................................................iv
第一章    前言……………………………………………………….......1
第二章    功率元件的發展與理論…………………………….....…......4
2.1橫向擴散場效電晶體的改良…………...…..........................4
2.1.1寄生效應的結構改進…............ ...................................5
2.1.2克爾克效應(Kirk Effect)…............................................5
2.1.3 RESURF結構…...... ......................................................6
2.1.4超接面結構(Super junction)….......................................7
2.1.5矽晶絕緣體結構 (Silicon on Insulator)….....................7

     2.2功率元件崩潰之機制.................... ..........................................7
         2.2.1基納崩潰（Zener breakdown ）.. ......................….....8
         2.2.2累增崩潰（avalanche breakdown）......………….......8
         2.3.3穿透型崩潰（Punch-through breakdown）..................9

      2.3衝擊游離化與放大係數………………………………...….11
2.4橫向雙擴散金氧半場效電晶體在關閉狀態之操作原理....12
2.5導通電阻........... .................... ........................... ....................8
2.5.1通道電阻…………………………………….………..13
2.5.2聚積電阻……... ……………………………………...14
2.5.3漂移電阻……………………………………………...14
第三章 元件製作與模擬分析…....…………....………...………...…..25
       3.1參數定義................................................................................25
         3.1.1崩潰電壓(breakdown voltage) ......................................25
         3.1.2導通電阻(on-resistance)……………………………….26
         3.1.3臨界電壓 (threshold voltage)………………………….27
         3.1.4效能指標(efficiency index)…………………………….28
      3.2HIGH-SIDE DDDMOSFET之製程步驟 ……………...…....28
         3.2.1高壓N型井(HVNW)製程…………..............................29
         3.2.2考慮High-side條件下之模擬……………................. ...30
         3.2.3 N型深埋層(N-buried layer)製程….. ………..……...….30
         3.2.4 N型深埋層(N-buried layer)位置對元件的影響…….....30
3.2.5 改善導通電阻之設計…………………………….…….31
第四章 量測結果與模擬比較……………………………………………45
4.1導通電阻(Ron)與崩潰電壓(BV)萃取………...........................45
4.2模擬與量測比較………............................................................45
         4.2.1烘烤效應(baking effect)………………………….…….45
         4.2.2緩衝氧化層(buffer oxide)………………………….......46
第五章 結論..............................................................................................50
參考文獻....................................................................................51

                                

[1] J. A. Appeals, and H. M. J. Vaes, “High-voltage thin layer devices (RESURF devices)”, IEDM Tech. Dig., pp. 238-239, 1979.
[2] B.J. Baliga, “Power Semiconductor Devices”,PWS. Publishing company, 1995. pp. 69
[3] Zahir Parpia, C. Andre T. Salama, “Optimization of RESURF LDMOS Transistors : An Analytical Approach” IEEE Trans. Electron Device, Vol. ED-37, No. 3, pp.789-795, 1990.
[4] S. M. Sze, “SEMICONDUCTOR DEVICES Physics and Technology”, Copyright 1981 by JWS, 2nd ed
[5] Jian-Meng, Shan-Gao, Jun-Ning Chen, Dao-Ming Ke, “The Analysis and Modeling of On-resistance in High-voltage LDMOS”, th ICSICT’06. 8th International Conference on Solid-State and Integrated Circuit
[6] M. Elwin, P. Holland, I. Anteney , J. Ellis, L. Armstrong, G. Birchby
and P. Igic, “Optimisation of 100V High Side LDMOS Using Multiple Simulation Techniques” Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on 14-18 June 2009 Page(s):104 - 107

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