摘要

在各種萃取有效通道長度的方法裡，偏移比例法(Shift and Ratio method)曾被認為是最準確且合理的萃取方法，這個萃取方法最重要的假設為短通道跟長通道的遷移率是相同的。但MOSFET元件尺寸持續不斷縮越小，為了元件效能最佳化設計，都一定有Halo/Pocket implant，來改善短通道效應以及防止”穿遂現(punchthrought)，並且我們常使用STI(Shallow trench isolation)來取代傳統的局部氧化(LOCOS)方式，以滿足高積成密度的要求，因為元件效能最佳化設計的需求，以上兩種結構(STI + Halo pocket implant)設計會明顯的改變遷移率的行為，使原本偏移比例法(Shift and Ratio method)的遷移率的假設條件已經不符合近代MOSFET元件遷移率行為，這樣當然無法準確地萃取近代MOSFET元件的有效通道長度。所以我們在這篇論文將會先檢視偏移比例法(Shift and Ratio method)的缺點，並修正其假設條件上的不正確性。我們觀察近代的MOSFET元件特性，發現源極與汲極在製程上因側面擴散造成Grade junction，我們必須考慮有因閘極造成的通道長度調變，我們將有效長度( )設為閘極電壓的函數似乎會更合理，其中 為源極到汲極 metallurgical junction的長度，且近代MOSFET元件效能最佳化設計都必定有 Halo/Pocket implant結構，所以我們就必須假設短通道元件的遷移率正比於長通道元件的遷移率( )，修正原有的偏移比例法(Shift and Ratio method)過大萃取有效通道長度的現象。
我們會比較原有的偏移比例法(Shift and Ratio method)和改良的偏移比例法(An improved Shift and Ratio method)萃取出來的結果，並以Medici模擬的通道長度(電流散開進入源極跟汲極與通道電流大小相同的位置)來檢視這兩種方法的準確性，並比較不同MOSFET元件結構，所萃取出來的有效通道長度。

參考文獻 Reference

[1]Rim, K.; Narasimha, S.; Longstreet, M.; Mocuta, A.; Cai, J.;” Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs”Electron Devices Meeting, 2002. IEDM '02. Digest. International , 8-11 Dec. 2002
[2]Yuan Taur “MOSFET channel length: extraction and interpretation”Electron Devices, IEEE Transactions on , Volume: 47 , Issue: 1 , Jan. 2000
[3]Taur, Y.; Zicherman, D.S.; Lombardi, D.R.; Restle, P.J.; Hsu, C.H.; Nanafi, H.I.; Wordeman, M.R.; Davari, B.; Shahidi, G.G.” A new shift and ratio' method for MOSFET channel-length extraction”Electron Device Letters, IEEE , Volume: 13 , Issue: 5 , May 1992
[4] B. J. Sheu and P. K. Ko, “A capacitive method to determine channel lengths for conventional and LDD MOSFET’s,” IEEE Electron Device Lett., vol. EDL-5, p. 491, 1984
[5] Ng, K.K.; Brews, J.R.; Measuring the effective channel length of MOSFETs Circuits and Devices Magazine, IEEE , Volume: 6 , Issue: 6 , Nov. 1990 Pages:33 – 38
[6] K. Terada and H. Muta, “A new method to determine effective MOSFET channel length,” Japan. J. Appl. Phys., vol. 18, p. 935, 1979.
[7] 6. J. G. J. Chem. P. Chang, R. F. Motta and N.Godinho, "A New Method lo Determine MOSFET Channel Length." IEEE Elect. Dev. Lett.. EDL-1(9). p. 170. 1980.
[8]P. 1. Suciu and R. L. Johnston."Experimental Derivation of the Source and Drain Resistance of MOS Transistors," IEEE Trans. Elect. Dev.. ED-27(9), p.l846. 1980.
[9] F. H. De La Moneda, H. N. Kotecha and M.Shatzkes. "Measurement of MOSFET Constants," IEEE Elect. Dev. Lett., EDL-3(1),p. 10.1982.
[10] K. L. Peng and M. A. Afromowitz, "An Improved Method to Determine MOSFET Channel Length." IEEE Elect. Dev. Lett.. EDL 3(12), p. 360, 1982.
[11]B. J. Sheu. C. Hu. P. K. Ko and F. C. Hsu."Source-and-Drain Series Resistance of LDD MOSFET's," IEEE Elect. Dev. Lett., EDL-5(9). p. 365.1984.
[12] K. -L. Peng, S. -Y. Oh. M. A. Afromowitz and J. L. Moll. "Basic Parameter Measurement and Channel Broadening Effect in
the Submicrometer MOSFET." Elect Dev.Leil..EDL-5(ll) IEEE p.473.1984.
[13] J. Whilfield, "A Modification on –An Improved Method to Determine MOSFET Channel Length,'" IEEE Elect. Dev. Lett., EDL-6(3).p. 109.1985.
[14] L. Chang and J. Berg. "A Derivative Method to Determine a MOSFET's Effective Channel Length and Width Electrically." IEEE Elect. Dev. Lett.. EDL-7(4). p. 229. 1986.
[15] G. J. Hu. C. Chang and Y. T. Chia. "Gate-Voltage-Dependent Effective Channel Length and Series Resistance of LDD MOSFET's."IEEE Trans. Elect. Dev., ED-34(12), p. 2469,1987.
[16] J. C. Guo, S. S. Chung, and C. C. Hsu, “A new approach
to determine the effective channel length and the drain and source series resistance of miniaturized MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, p.1811, 1994.
[17] Limitations of shift-and-ratio based Leff extraction techniques for MOS transistors with halo or pocket implants
van Meer, H.; Henson, K.; Lyu, J.-H.; Rosmeulen, M.; Kubicek, S.; Collaert, N.; De Meyer, K. Electron Device Letters, IEEE , Volume: 21 , Issue: 3 , March 2000 Pages:133 – 136
[18] Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.:On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration;Electron Devices, IEEE Transactions on , Volume: 41 , Issue: 12 , Dec. 1994 Pages:2357 – 2362
[19] Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics Miyamoto, M.; Ohta, H.; Kumagai, Y.; Sonobe, Y.; Ishibashi, K.; Tainaka, Y.;Electron Devices, IEEE Transactions on , Volume: 51 , Issue: 3 , March 2004
Pages:440 - 443