時脈信號在現今的電子產品中扮演著不可或缺的角色，不論是通訊、儀器或者是智慧型手機都需要時脈產生電路才能正常運作。這些時脈電路必需藉由石英振盪器這個參考頻率源才能產生時脈。然而石英晶體振盪器擁有大面積、高功率消耗、無法與CMOS製程相容等缺點，因此過去三十年來各界學者專家都試圖尋找能替代石英振盪器的方案。
近年來被提出的解決方法有MEMS振盪器、QMEMS振盪器、LC振盪器以及具有電壓回授控制之弛張振盪器。但是MEMS、QMEMS等方法無法與CMOS電路整合；LC振盪器消耗功率過大；弛張振盪器無法避免因製程變異所導致內部電路不匹配、責任週期不為50%的問題。因此我們致力於研製以CMOS標準製程實現低功率消耗、具備精準責任週期之參考頻率源。
在本篇研究當中，我們透過將兩組充放電路徑簡化為一組路徑的方式來解決電路不匹配的問題，並且藉由加上一個除頻電路增進責任週期的精準度。此晶片使用 TSMC 0.18 μm 1P6M標準製程實現，模擬與量測結果皆顯示出此振盪器輸出波形之責任週期可精準的達到50%，達成節省面積、低功率消耗、能與CMOS整合並且具備精準責任週期之參考頻率源。

Clock signal plays an important role in nearly all consumer electronics. Electronic platforms ranging from communications, instruments to smart phone need clock generation to work properly. Additionally, most of these circuits require crystal oscillators (XO) serving as the frequency reference. Nevertheless, quartz crystal possesses some disadvantages such as large area, high power consumption and cannot be integrated into microelectronic process technology. For these reasons, researchers had been devoting themselves to exploiting technologies to replace quartz over the past thirty years.
Recently, several methods have been proposed to solve above mentioned problems, including MEMS oscillators (MOs), QMEMS, LC oscillators and relaxation oscillator with voltage average feedback circuits. However, MOs and QMEMS remain the challenge in process integration; LC oscillators consume too much power and chip area; relaxation oscillator is subject to mismatch caused by manufacturing process which would induce inaccurate duty cycle. Considering these defects collectively, we aimed to develop an integrated frequency source with accurate duty cycle and low power consumption.
In this paper, we proposed a method to avoid mismatch in relaxation oscillator, that is, to simplify the two charging and discharging paths as one single path. Furthermore, we improved the accuracy of duty cycle by employing a divider in the oscillator. The chip in this work was fabricated in the TSMC 0.18 μm 1P6M process. Both of the simulation and measurement results show that such approach efficiently enhances the accuracy of duty cycle to 50%, achieves small chip area and low power dissipation, and can be realized with standard CMOS processes.

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