摘要
奈米晶記憶體之構想是在1996年IBM公司研究團隊所提出,最早是採用在SiO2介電層中插入奈米尺度的矽晶顆粒陣列,後來考慮到奈米晶粒所形成的量子井矽基版之能階差問題,建議改為Ge或金屬奈米粒子,另外有關介電層材料,也有人提議採用high-k氧化物來取代SiO2。有關在SiO2中製作半導體(Si,Ge)或金屬(Au,Pt,W等)奈米晶粒夾層技術,大多採用化學氣相沉積、離子植入、電子束沉積或共鍍等方法。這些製程技術雖然各見優點,但有一共同缺點就是製作出來的奈米粒子的粒徑較大,分佈也較不均勻。
在實驗室的研究之下,發現以磁控濺鍍白金,若在Ar電漿中加入氧氣,會鍍出PtOx薄膜,此PtOx薄膜並不穩定,會在中溫(300~500℃)熱處理下還原分解回純白金,而利用PtOx之化學不穩定性,以RF濺鍍在MOS結構的閘極介電層中插鍍一層超微PtOx,再以熱處理還原成粒徑在2~3nm之白金奈米粒子陣列,此PtOx超微薄膜是以自組裝方式分解成白金奈米晶陣列,粒子大小與分佈相當均勻。
除了奈米晶粒之大小與分佈外,控制層與穿隧層的材料與結構,亦會對奈米晶記憶體的功能,包括記憶持久性及存取速度,操作電壓等會有很大的影響,在我的論文當中將探討閘極介電層材料結構的影響。奈米晶記憶體的結構為電極/控制層/奈米晶/穿隧層/基版通道,此MOS電容可視為控制層電容Cco與穿隧層電容Cto串聯,由於奈米晶之充放電取決於穿隧層所受電壓,而此電壓Vto與施加於閘極的電壓Vg的關係為Vto=Vg．Cco/(Cco+Cto),因此在同樣的介電層厚度下,採用較高介電係數的控制層材料,對特定的Vto,所需的Vg較低,固有利於操作電壓的降低,同時也將比較不同閘極材料下,對於漏電流的影響,及對於侷限電子的持久性(retention)的比較。

REFERENCE
1.電子與材料雜誌 第24期 奈米電子元件;張鼎張,顏碩廷,劉柏村 ; 單電子電晶體;胡淑芬
2. 1. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory”, Appl. Phys. Lett. 68, 1377(1996).
3. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals”, J. Appl. Phys. 84, 2358(1998).
4. L. Guo, E. Leobandung, and S. Y. Chou, “A silicon single-electron transistor memory operating at room temperature”, Science 275, 649(1997).
5. I. Kim, S. Han, K. Han, J. Lee, and H. Shin, “Room temperature single electron effects in a Si nanocrystal memory”, IEEE Electron Device Letters 20(12), 630(1999).
6. M. Saitoh, E. Nagata, and T. Hiramoto, “Large memory window and long charge-retention time in ultranarrow channel silicon floating-dot memory”, Appl.
Phys. Lett. 82, 1787(2003).
7. Y.-C. King, T.-J. King, and C. Hu, “Charge-trap memory device fabricated by oxidation of Si1-xGex”, IEEE Trans. Electron Devices 48, 696(2001).
8.Y.-C. King, T.-J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEDM Tech. Dig., 98(1998).
9.Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—part Ⅰ: device design and fabrication”, IEEE Trans. Electron Devices 49, 1606(2002).
10.Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—part Ⅱ: electrical and characteristics”, IEEE Trans. Electron Devices 49, 1614(2002).
11.D. Halley, G. Norga, A. Guiller, J. Fompeyrine, J. P. Locquet, U. Drechsler, H. Siegwart, and C. Rossel, “Charging effects on the carrier mobility in silicon-on-insulator wafers covered with high-k layer” J. Appl. Phys. 94, 6607(2003).
12.H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nano-crystal memory”, IEEE Trans. Electron Devices 43, 1553(1996).
13.S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories”, Appl. Phys. Lett. 69, 1232(1996).
14.N. Takahashi, H. Ishikuro, and T. Hiramoto, “Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates”, Appl. Phys. Lett. 76, 209(2000).
15.E. Kapetanakis, P. Normand, and D. Tsoukalas, “Room temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis”, Appl. Phys. Lett. 80, 2794(2002).
16.T. Ohzone, T. Matsuda, and T. Hori, “Erase/write cycle test of n-MOSFET’s with Si-implanted gate-SiO2”, IEEE Trans. Electron Devices 43, 1374(1996).
17.C. Lee, Z. Liu and E. C. Kan, “Investigation on process dependence of self-assembled metal nanocrystals”, Mater. Res. Soc. Symp. Proc. 737, F8.18.1(2003).
18.C. Lee, A. Gorur-Seetharam and E. C. Kan, “Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single-and double-layer metal nanocrystals”, IEDM Tech. Dig., 557(2003).
19.L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 81, 3639(2002).
20.V. Ho, L. W. Teo, W. K. Choi, W. K. Chim, and M. S. Tay, “Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure”, Appl. Phys. Lett. 83, 3558(2003).
21.W. K. Choi and W. K. Chim, “Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 80, 2014(2002).
22.V. Ho, M. S. Tay, C. H. Moey, L. W. Teo, W. K. Choi, W. K. Chim, C. L. Heng, and Y. Lei, “Electrical characterization of a trilayer germanium nanocrystal memory device”, Microelectronic Engineering 66, 33(2003).
23.T. Hiramoto, “To fill the gap between Si-ULSI and nanodevices”, International Journal of High Speed Electronics and Systems 10 (1), 197(2000).
24.H. Ishikuro and T. Hiramoto, “Influence of quantum confinement effects on single electron and single hole transistors”, IEDM Tech. Dig., 119(1998).
25.S. Huang, S. Banerjee, R. T. Tung, and S. Oda, “Quantum confinement energy in nanocrystalline silicon dots from high-frequency conductance measurement”, J. Appl. Phys. 94, 7261(2003).
26. 半導體元件.(solid state electronic devices),Ben G. Streetman.Sanjay Banerjee
吳孟奇,洪勝富,連振炘,龔正 譯
27.P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, in proceedings of the IEEE, number 8, p. 1248(1997).
28.A. K. Sharma, “Semiconductor memories”, IEEE press, New Jersey, 1997.
29.S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory”, Appl. Phys. Lett. 68, 1377(1996).
30.B. Prince, “Emerging Memories – Technologies and Trends” by Kluwer Academic Publishers, p. 133(2002).
31.S. J. Baik, S. Choi, U-In Chung, and J. T. Moon, “High speed and nonvolatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier”, IEDM Tech. Dig., 545(2003).
32.K. W. Guarini, C. T. Black, Y. Zhang, I. V. Babich, E. M. Sikorski, and L. M. Gignac, “Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly”, IEDM Tech. Dig., 541(2003).
33.R. Muralidhar, R. F. Steimle, M. Sadd, R. Rao, C. T. Swift, E. J. Prinz, J. Yater, L. Grieve, K. Harber, and B. Hradsky, “A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory”, IEDM Tech. Dig., 601(2003).
34.T. Ohzone, T. Matsuda, and T. Hori, “Erase/write cycle test of n-MOSFET’s with Si-implanted gate-SiO2”, IEEE Trans. Electron Devices 43, 1374(1996).
35.G. Puzzilli, D. Caputo, and F. Irrera, “Fast and reliable tunnel programming of nanocrystal nonvolatile memories”, IEEE Trans. Electron Devices 51, 1205(2004).
36.J. K. Kim. H. J. Cheong, Y. Kim, J. Y. Yi, H. J. Bark, S. H. Bang, and J. H. Cho, “Rapid-thermal-annealing effect on lateral charge loss in metal-oxide-semiconductor capacitors with Ge nanocrystals”, Appl. Phys. Lett. 82, 2527(2003).
37.T. Hiramoto, “To fill the gap between Si-ULSI and nanodevices”, International Journal of High Speed Electronics and Systems 10 (1), 197(2000).
38.Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals”, J. Appl. Phys. 84, 2358(1998).
39.H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nano-crystal memory”, IEEE Trans. Electron Devices 43, 1553(1996).
40.S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories”, Appl. Phys. Lett. 69, 1232(1996).
41.M. Saitoh, E. Nagata, and T. Hiramoto, “Large memory window and long charge-retention time in ultranarrow channel silicon floating-dot memory”, Appl. Phys. Lett. 82, 1787(2003).
42.N. Takahashi, H. Ishikuro, and T. Hiramoto, “Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates”, Appl. Phys. Lett. 76, 209(2000).
43.E. Kapetanakis, P. Normand, and D. Tsoukalas, “Room temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis”, Appl. Phys. Lett. 80, 2794(2002).
44.C. Lee, Z. Liu and E. C. Kan, “Investigation on process dependence of self-assembled metal nanocrystals”, Mater. Res. Soc. Symp. Proc. 737, F8.18.1(2003).
45.C. Lee, A. Gorur-Seetharam and E. C. Kan, “Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single-and double-layer metal nanocrystals”, IEDM Tech. Dig., 557(2003).
46.Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—part Ⅰ: device design and fabrication”, IEEE Trans. Electron Devices 49, 1606(2002).
47.Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—part Ⅱ: electrical and characteristics”, IEEE Trans. Electron Devices 49, 1614(2002).
48.L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 81, 3639(2002).
49.V. Ho, L. W. Teo, W. K. Choi, W. K. Chim, and M. S. Tay, “Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure”, Appl. Phys. Lett. 83, 3558(2003).
50.W. K. Choi and W. K. Chim, “Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 80, 2014(2002).
51.V. Ho, M. S. Tay, C. H. Moey, L. W. Teo, W. K. Choi, W. K. Chim, C. L. Heng, and Y. Lei, “Electrical characterization of a trilayer germanium nanocrystal memory device”, Microelectronic Engineering 66, 33(2003).
52.H. Ishikuro and T. Hiramoto, “Influence of quantum confinement effects on single electron and single hole transistors”, IEDM Tech. Dig., 119(1998).
53.P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, in proceedings of the IEEE, number 8, p. 1248(1997).
54.R. Ohba, “Nonvolatile Si quantum memory with self-aligned doubly-stacked dots”, IEDM Tech. Dig., 313(2000).
55.I. Kim, “Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics”, IEDM Tech. Dig., 111(1998).
56. 半導體元件.(solid state electronic devices),Ben G. Streetman.Sanjay Banerjee
吳孟奇,洪勝富,連振炘,龔正 譯
57.白金奈米晶粒於金屬-氧化物-半導體結構中對非揮發性懸浮閘極記憶體應用之研究,清華大學博士論文,曾駿逸博士
58.C.Lee,A.Gorur-seetharam and E.C.Kan,Tech.Dig.-Int.Electron Devices Meet,557(2003)
59.Y.Shi,K.Saito,H.Ishikuro,and T. Hiramoto,J. APPl.Phys.84,2358(1998)
60.T.Futatsugi et al,Fujitsu,1998
61. J. B. Kim, D. R. Kwon, K. Chakrabarti, and Chongmu Leea), K. Y. Oh, J. H. Lee
“Improvement in Al2O3 dielectric behavior by using ozone as an oxidant for the atomic layer deposition technique”, JOURNAL OF APPLIED PHYSICS VOLUME 92, NUMBER 11 1 DECEMBER 2002
62.化學氣相沉積二氧化鋯閘極介電薄膜的結構與電性之研究, 清華大學博士論文,黃世賢博士
63.奈米極金粒子型單電子電晶體研發現況,胡淑芬,吳永俊.黃調元,劉如熹,葉儒林
64.M. Dai, K. Chen, X. Huang, L. Wu ,L. Zhang ,F. Qiao, W. Li, and K. Chen,”Formation and charfing effect of Si nanocrystals in a-SiNz/a-Si/a-SiNx structures”,J.Appl.Phys,95,640(2004)
65.S.Huang ,S. Banerjee ,R.T. Tung ,and S. Oda,” electron trapping ,storing ,and emission in nanocrystalline Si dots by capacitance-voltage and conductance-voltage measurement” ,J .Appl.Phys.93,576 (2003)
66.E.H.Nicollian and A. Goetzberger, Bell Syst.Tech.J.46,1005(1967)