近年來快閃記憶體的應用越來越廣泛，例如數位相機、mp3播放器、手機、大姆哥等等~~，所以快閃記憶體可靠度的問題越來越受到重視，我們設計快閃記憶體cell電流的內建量測電路，主要的應用有二個：第一個應用是在快閃記憶體剛出廠時cell 電流分佈的特性分析；第二個應用是在快閃記憶體cell使用期限的偵測，因為快閃記憶體在長時間使用之後，電子從集極(drain)入射(injection)到浮動閘極(floating gate)，或是電子從浮動閘極退回(rejection)到集極的能力降低，而造成cell 電流的偏移。當偏移的電流超過安全範圍時，將導致感應放大器(sense amplifier)資料誤判，所以我們可以籍由觀察cell電流的變化而去決定這個cell的使用期限。目前量測快閃記憶體陣列的cell電流所使用的方法是使用外部精密昂貴的測試設備，我們提出了一個針對快閃記憶體的內建式cell電流量測電路，目的是為了降低量測成本並且能夠隨時偵測cell的電流，我們利用簡單的串疊電流鏡以及改良式的current mode的電流類比數位轉換器完成電流量測電路，我們提出的這個電路也能夠根據不同的快閃記憶體cell電流分佈，而選用不同的參考電流(reference current)，而能避免直接量測小電流，進而提高量測速度。我們設計的量測電路量測的範圍為25.6mA的寬廣量測範圍，最大的參考電流可設為12.8mA，解析度能達到0.1mA，量測時間為250ns加上感應放大器的感應時間，一般來說可以在260ns完成量測。我們使用TSMC 0.25mm標準的 tsmc CMOS製程，用Hspice模擬結果。

The way to measure the current of memory cell nowadays is to use precision, high-cost automatic test equipments. The method proposed here uses an embedded measurement circuit to obtain cell current for flash memory such that not only the measurement cost can be reduced but also current is detected in any time slot. The maximum measure range of the proposed embedded measurement circuit for flash memory cell current is 25.6uA with resolution as accurate as 0.1uA, so that the measurement time for a flash memory cell can be completed under 260ns. The HSPICE simulations of proposed embedded measurement unit use a 0.25um TSMC CMOS process technology.

[1] P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash memories”, 1999, Kluwer Academic Publishers.

[2] Z. Jun, “Flash memory technology development”, Proc. of 6th IEEE International Conference on Solid-State and Integrated-Circuit Technology, vol. 1, Oct. 2001, pp. 189-194.

[3] “IEEE standard definitions and characterization of floating gate semiconductor arrays”, IEEE Std 1005-1998 , 9 Feb. 1999.

[4] J. P. A. Carreira and J. E. Franca, “High-speed CMOS current comparators” Proc. of IEEE International Symposium on Circuits and Systems, vol. 5, June. 1994, pp.731-734

[5] D.G. Nairn and C.A.T. Salama, “Current-mode algorithmic analog-to-digital converters” , IEEE Journal of Solid-State Circuits , vol. 25, Issue: 4, Aug. 1990, pp. 997 – 1004.

[6] Z. Ciota, M. Jankowski and A. Napieralski, “Design of A/D converters using current-mode standard cells”, Proc. of IEEE International Conference on Electronics Circuits and Systems, Volume: 1 , vol.1, Dec. 2000, pp. 24 – 27.

[7] G.. Giustolisi, G.. Palumbo and S. Pennisi, “Resolution of a current-mode algorithmic analog-to-digital converter”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, Issue. 10, Oct 2002, pp. 1480-1486.

[8] T. Tanzawa , Y. Takano, T. Taura and S. Atsumi, “Design of a sense circuit for low-voltage flash memories”, IEEE Journal of Solid-State Circuits, vol. 35, Issue. 10, Oct 2000, pp. 1415-1421.

[9] A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas and A. Arapoyanni, “A new flash memory sense amplifier in 0.18 μm CMOS technology”, Proc. of the 8th IEEE International Conference on Electronics Circuits and Systems, vol 2, Setp 2001, pp. 941-944.

[10] C. Papaix and J. M. Daga, “A new single ended sense amplifier for low voltage embedded EEPROM non volatile memories”, Proc. of IEEE International Workshop on Memory Technology Design and Testing, July 2002, pp. 149-153.

[11] P. Pavan, L. Larcher, M. Cuozzo, P. Zuliani and A. Conte,“A complete model of E/sup 2/PROM memory cells for circuit simulations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, Issue. 8, Aug 2003, pp.1072-1979.