摘要

高介電係數介電材料(high-k)與矽基底鍵結不完全以及材料本身的差異，一般認為是造成high-k閘電晶體電特性退化的主因之一，因此如何準確且快速地量測界面陷阱和本體缺陷的數量及分佈，顯然是一個相當有價值的研究工作。本文中簡介了數個以CP量測 (charge-pumping, CP , measurement) 為基礎所發展出來的量測技術，並針對實際量測到的現象提供原理說明。傳統調變脈衝上升/下降緣 (rise/fall times of gate pulse) 的CP量測技術，已成功地應用在探測high-k閘電晶體內部界面陷阱密度及其能量分佈。並且為了有效偵測邊緣缺陷 (border trap)，本文提出一套以變化頻率牽動汲引電荷Qcp (即Icp/f) 產生變化為基礎的數學計算模式，用以估算在high-k介電層內邊緣缺陷縱深分佈。另外，就邊緣缺陷對CP量測的影響以及邊緣缺陷本身特有的行為也將逐一被介紹。並且從實際的邊緣缺陷縱深分佈結果可以清楚發現，在high-k堆疊閘介電層內部的本體缺陷分佈是相當不均勻的。脈衝振幅 (amplitude of gate pulse) 增加以及電應力施加後介電層內部因熱載子所衍生的缺陷對整体CP量測的影響，也將在本文中被討論。從實驗結果來看，high-k介電層內部固有的弱鍵 (weak bonds) 似乎容易因為電應力施加而捕陷電荷形成氧化層缺陷電荷，並造成一定程度的臨界電壓漂移。此外，電應力所衍生的邊緣缺陷可能不是傳統所認知固定位置的缺陷捕陷中心 (fixed trapping center)，而是一可移動的缺陷其反映出電性的行為類似電洞。在考慮了變化頻率以及變化脈衝振幅兩種不同的CP量測方式，變頻的方式顯示較為合適探究邊緣缺陷以及延展穿遂縱深。在導入有關邊緣缺陷載子穿遂的影響之後，本文也提出一套新穎的CP量測技術用以觀測high-k閘電極元件內部淺界面缺陷空間及能量分佈。從量測結果顯示有相當低的邊緣缺陷密度存在於HfOxNy/SiO2界面中間的過渡層，而這可能的原因是這層過渡層具有較好的材料鍵結所致。

Abstract

High-k dielectric constant (high-k) material has been proposed to replace the conventional silicon dioxide as gate dielectrics of metal-oxide-semiconductor (MOS) devices in the near future. However, the characteristic and extent of charge trapping in the interfacial layer between high-k dielectric and silicon have been reported to affect strongly the electrical characteristics of high-k gated MOS devices. Hence, providing an accurate and quick measurement for density and distribution of interface and bulk traps is believed to be a valuable research topic. This work proposes several measurement techniques based on the principle of charge pumping (CP) and provides some discussion in depth for measurement results. A CP technique with varying fall and rise times has been successfully applied to determine the mean capture cross-section and the energy distribution of the interface-trap density Dit(E) in high-k gated MOS devices. Also, in order to further study the border traps near the high-k/Si interface, a calculation model based on the variation of the charge pumped per cycle (Qcp) with frequency has been proposed to estimate the depth profile of border trap in the high-k dielectric. Besides, the influence of border traps on CP measurement and its unique behavior are also investigated. It is found that there is a non-uniform distribution of bulk trap density existing in high-k gate stack dielectric. Moreover, the effects of amplitude of gate pulse and electrical stress-induced traps by a CP measurement are studied. Measurement results indicate that the weak bonds in high-k gate dielectric are easily trapped by charges after stressing; thus, stress results in a large threshold voltage (Vth) shift. It is also observed that the stress-induced border trap is probably not a fixed trapping center but a mobile defect like hole. By taking into account on the effect of carrier tunneling in slow oxide traps, a promising CP technique has been proposed to obtain a clear observation on the spatial and energy distribution of the near-interface traps in the gate dielectric of high-k gated MOSFETs. The CP method with varying-frequency has been shown to be more effective for probing border traps than that with varying-amplitude. Border-trap density is relatively lower in the HfSiON layer due to its better bonding.

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