現今的半導體記憶體種類繁雜，反及閘型快閃記憶體卻有著其重要的角色扮演。由於其陣列的排列方式，反及閘型快閃記憶體可以達到極高的密度，這在當今可攜式電子產品蓬勃發展、大量資料存取應用中，是有著不可取代且重要的設計考量。並且因為其容量大，因此佔整個晶片非常大的面積，如果可以降低反及閘型快閃記憶體的製造成本，即可大幅增加競爭力。
在目前的系統應用晶片中，內嵌式的反及閘型快閃記憶體需要高電壓使電子進入懸浮閘極來完成〝寫入〞的機制，而電荷幫浦則普遍地用在晶片內部以產生一個比供應電源更高的正電壓或比零更低的負電壓。然而，因為電荷幫浦產生的高電壓會有〝漣漪〞的現象，會在目標電壓上下的震動，造成反及閘型快閃記憶體在〝寫入〞機制時的垂直電場強度改變，影響到反及閘型快閃記憶體〝寫入〞的電子數量，因此對記憶體元件來說，邏輯1和邏輯0的差異性會變小，或者是，造成〝寫入〞程度不準的問題，進而造成記憶體資料存取錯誤。
我們提出一電荷幫浦輸出偵測機制，當輸出電壓的漣漪電壓大到某個程度時，會經由一回授電路來降低電荷幫補的幫浦能力，這樣既能保持電荷幫浦原來的啟動時間，亦能降低穩態時的電荷幫浦的漣漪電壓。

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