本論文提出了一個十一位元低功耗連續近似類比數位轉換器，可應用於無線通訊系統，並且使用校正與每周期比較兩位元之技術(2b/C)。
所提出的類比數位轉換器為了實現較高的操作速度，使用了每周期比較兩位元的方法，得到兩倍的操作速度，由於此方法需要使用三個比較器，其偏移會導致線性度下降，這裡使用了比較器偏移校正電路來消除三個比較器的偏移並且得到了明顯改善。為了實現每周期比較兩位元的方法，電路中有一組額外的數位類比轉換器(DAC)用來產生參考電壓，為了解決兩組數位類比轉換器之不匹配以及比較器的動態偏移，在數位類比轉換器中加入了冗餘位元，此方法比起二分搜尋法有較大的搜索範圍，因此能容忍比較過程中一定大小的錯誤量，。此外，本論文還提出了一個兩階段式數位類比轉換器(two-step DAC)切換方法來降低耗能，藉由組合每周期比較兩位元以及每周期比較一位元的切法，可以降低用來產生參考電壓之數位類比轉換器的解析度，因此能降低切換功耗與面積，改善能源效率。
此架構使用台積電標準90 奈米1P9M 互補式金氧半導體製程製作，晶片面積為160 x 550um2，操作電壓0.9 伏特，在一千萬赫茲的取樣頻率及一萬赫茲的輸入訊號頻率下得到SNDR 為55.3dB 對應到8.9 個有效位元，功率消耗為108微瓦，等校的figure of merit (FoM) 22.6fJ/conversion-step。

This thesis proposed an 11-bit power-efficient 2 bits per cycle (2b/C) successive approximation register (SAR) analog-to-digital converter (ADC) with calibration for wireless communication systems.
To achieve a higher operation speed, a 2b/cycle topology is adopted in this work. The Multi-bit per cycle ADC requires multiple comparators and reference voltage to perform the technique. To realize the 2b/C method, an additional digital-to-analog converter (DAC) is needed to generate a reference voltage. The mismatch between the reference DAC and signal DAC will degrade the linearity. The solution is to add redundancy bits to tolerate the error during the AD conversion. Since the comparator offsets will cause linearity error and degradation of ADC performance, an offset calibration is used to cancel the offsets and keep an acceptable linearity. Besides, a 2-step DAC configuration is proposed to reach a lower power and area. Combine the 2b/C DAC and 1b/C DAC, the resolution of reference DAC can be reduced. Hence, the DAC power and area are decreased.
This prototype was fabricated by TSMC 90nm 1P9M CMOS technology and the core area is 160x550um2. At a 0.9V supply and a 10MS/s sampling rate with a input frequency of 10kHz, the ADC achieves a SNDR of 55.4dB and a corresponding ENOB of 8.9b. The power consumption is 108 W and it achieves a FoM of 22.6 fJ/conv-step.

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