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研究生： 黃俞傑
Yu-Chieh Huang
論文名稱： IEEE 1500-Based Delay Test Framework for At-Speed Testing of Multiple Clock Domains
基於IEEE1500且支援多個時脈域之自動化延遲錯誤測試架構
指導教授： 張慶元
Tsin-Yuan Chang
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 52
中文關鍵詞： 延遲測試 、多時脈
外文關鍵詞： at-speed, multiple clock domains
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    • Rapid advance of semi-conductor technology and the increasing speed of system clocks make designs with multiple clock domains and further integration of these designs into a System-on-Chip (SOC) feasible. The IEEE std. 1500 has been enhanced to not only be capable of testing the functionality but also support at-speed testing of each embedded cores in SOC designs. However, previous works on designing the on-chip clock controllers only aim at the at-speed testing of single clock domain but fail to verify the corresponding timing specifications of clock-crossing domains. In addition, lacking the controllability of test wrapper makes these controllers unable to be integrated into IEEE 1500-based test environment. In this paper, an IEEE 1500-based at-speed testing clock controller that can support at-speed testing of multiple clock domains is proposed. Experimental results show a successful application to 1500-wrappered intellectual property (IP) cores with low area overhead.

    在半導體產業技術的高度發展之下，晶片中所擁有的電晶體個數隨著製程技術的提升呈現出一個高速的成長趨勢，也使原本只擁有單一功能的晶片可以將一個完整的系統置入其中，這就是所謂的系統晶片(System on Chip)。而為了提升靈活性，設計有著多時脈域的系統晶片也越來越受歡迎。在另依方面，隨著操作頻率的提升，許多與時間有關的問題以及所造成的錯誤也變的越趨嚴重，其中我們將針對因延遲所造成的錯誤做一個討論，稱之為延遲錯誤測試(Delay Fault Testing) 。
    對系統晶片而言，目前已有一套關於系統晶片測試的標準存在，但在這套標準當中並未對延遲錯誤測試制定出一套規範，為了使用整個系統晶片測試標準更加的完善，試圖在這套標準之下將延遲錯誤測試的功能置入其中，為了達到這個目的，先前的研究提出了一個時脈控制器來產生延遲錯誤測試所需要的連續的系統時脈，並以一套完善的流程來完成整個延遲錯誤測試。但是先前的時脈控制器，主要是針對單一時脈域的延遲錯誤測試，在對於多時脈域且跨時脈域的延遲錯誤測試上不能產生測試所需要的系統時脈，所以缺乏在多時脈域的錯誤測試功能，因此在此篇論文中，我們提出一個能夠支援多時脈域錯誤延遲測試的時脈控制器，並驗證其正確性以確保整個測試的可靠度及準確性，而在面積的消耗上也不會隨著時脈域的增加有次方性的增長。

    List of Contents 誌謝…………………………………………………………………… I Abstract……………………………………………………………….. II 中文摘要……………………………………………………………… III 目錄…………………………………………………………………… IV List of Contents……………………………………………………….. XII List of Figures………………………………………………………… XIV List of Tables………………………………………………………...... XVI Chapter 1. Introduction……………………………………………... 1 Chapter 2. Preliminary…….………………………………………... 4 2.1 IEEE 1500 Overview………….………………………… 4 2.1.1 Core Test Language…………………..…………… 4 2.1.2 Scalable Core Test Architecture…………………… 5 2.2 At Speed Testing Issues……………...…...……………… 7 2.2.1 Single Clock At-Speed Testing……………………. 7 2.2.2 Multiple Clocks At-Speed Testing………………… 9 2.3 Previous Works………………………………………….. 12 2.3.1 A Smart Delay Testing Framework based-on IEEE 1500 [2]……………………………………………. 12 2.3.2 An On-Chip Test Clock Control Scheme for Multi- Clock At-Speed Testing [5]……………….............. 16 Chapter 3. Modification…………………………………………….. 20 3.1 Introduction……………….…...………………………… 20 3.2 Wrapper Boundary Register Modification...…….………. 22 3.3 Control Circuit Modification………….……………….… 25 Chapter 4. Proposed Delay-Test-Aware Clock Controller………….. 27 4.1 The Proposed Architecture…….………………………… 27 4.2 Proposed Signal Controller…….………………………... 29 4.3 Enhanced Delay-Test-Aware Clock Controller………….. 29 4.3.1 Clock Gating and Switching Circuit………………. 30 4.3.2 The Control Cells………………………………….. 32 4.3.3 The N-Stage Delay Registers……………………… 38 4.3.4 Proposed Delay-Test-Aware Clock Controller…….. 40 Chapter 5. Case Study………………………………………………. 42 5.1 Integration of the Proposed Embedded At-Speed Clock Control Mechanism into 1500-Wrappered Cores……….. 42 5.2 Area Comparison of the Clock Controllers……………… 47 Chapter 6. Conclusions & Future Works…………………………… 48 6.1 Conclusions……………………………………………… 48 6.2 Future Works…………………………………………….. 49 Bibliography………………………………………………………….. 50 List of Figure Fig. 2.1 IEEE 1500 Wrapper components……………………….. 6 Fig. 2.2 (a) Launch-off-shift and (b) Launch-off-capture............... 8 Fig. 2.3 Intra-clock logic and Inter-clock logic………………..… 10 Fig. 2.4 Types of launch-capture pairs for at-speed testing of multiple clock domains……………………………….… 11 Fig. 2.5 Delay-Test-Aware Clock Controller……….…………..... 12 Fig. 2.6 The state diagram of the original TAP controller….……. 14 Fig. 2.7 The state diagram of the modified TAP controller in [2]….................................................................................. 14 Fig 2.8 Simulation of the Delay Fault Testing in [2]……………. 16 Fig 2.9 Architecture if the test clock control scheme in [5]……... 17 Fig 2.10 Structure of clock generator in [5]……………………… 18 Fig 2.11 Timing diagram of the clock generator in [5]…………… 19 Fig. 3.1 Regular wrapper input cell in [1], [11]……..……….…... 21 Fig. 3.2 Enhanced wrapper boundary register in [12]………..….. 22 Fig. 3.3 IEEE 1500 WBR………………………………………… 24 Fig. 3.4 Input WBR in [2]………..……………..………………... 24 Fig. 3.5 Synchronous Control………………………………..…... 26 Fig. 4.1 The at-speed clock control mechanism for at-speed testing of multiple clock domains……………………….. 28 Fig. 4.2 Types of launch-capture pairs for at-speed testing of multiple clock domains…………………………………. 28 Fig. 4.3 Clock Gating Circuit……………………………………. 31 Fig. 4.4 Clock switching circuit……………….............................. 31 Fig. 4.5 The FSM_T…………………………………………..…. 34 Fig. 4.6 The FSM_N…………………………………………..…. 35 Fig. 4.7 The FSM_N2……………………………………………. 35 Fig. 4.8 Waveform of slow-to-fast at-speed testing…………..…. 37 Fig. 4.9 Waveform of fast-to-slow at-speed testing…………..…. 38 Fig. 4.10 The N-stage delay registers…………..…………………. 39 Fig. 4.11 Waveforms of Generation of Two Normal Clock Pulses 40 Fig. 4.12 Delay-test-aware clock controller for at-speed testing of multiple clock domains…………………………………. 41 Fig. 5.1 Simulation of the fast-to-slow at-speed testing…………. 44 Fig. 5.2 Simulation of the fast-to-slow at-speed testing with different timing interval…………………………………. 45 Fig. 5.3 Simulation of the slow-to-fast at-speed testing…………. 46 List of Tables Table 5.1 The At-Speed Testing Sequences…..…………………… 43 Table 5.2 Area Comparison of the Clock Controller (NAND2)…... 47

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