FPGA在IC設計的功能驗證及原型上(Prototyping)早已被廣泛地使用著。由於它具備可以重複規劃的特性(Configurability)，使得它也被大量應用在網路、訊號處理等方面。今日伴隨著深次微米製程技術的進步，FPGA可以容納更大且更快的設計，但這也同時使得影響電路效能的延遲錯誤(Delay Fault)越加地明顯且嚴重。因而關於FPGA的延遲錯誤測試便顯得日益重要。此外由於FPGA內部超過80%的電晶體都屬於內部繞線(Interconnect)，所以我們所提出來的方法將專注在FPGA內部繞線的延遲錯誤上。
由於可重複規劃的特性，在FPGA上實現內建自我測試(BIST)的電路不僅不需要付出太多額外的代價，並且可以避免使用到過於昂貴的測試機台(ATE)。因而在這篇論文中我們針對FPGA內部繞線的延遲錯誤提出一個內建自我測試的方法。我們所提出來的BIST方法不僅可以作到即時測試(At-Speed Testing)，還可以在不受時脈歪斜(Clock Skew)影響的情況下，測試完大部分的元件。此外由於我們選取最短的受測路徑(Path Under Test)，因而對延遲錯誤將有很好的偵測能力(Detectability)。另外由於這個方法與使用者的電路無關，因而這個方法將可以應用在FPGA的製造測試上。
在實驗的部分，我們使用Xilinx Spartan系列的FPGA架構來驗證我們的BIST方法，並且使用一個高效率的FPGA Fault Simulator來審視我們方法的良窳。在我們的實驗中，即便是在眾多的延遲缺陷(Delay Defect)的影響下，我們的錯誤涵蓋率(Fault Coverage)依然超過98%。所需的Test Configuration僅36個，而全部的測試時間將近6.46秒。

As users implement more circuits operating at high speed in FPGA and more defects affect the delays with the advances of VLSI technology, FPGA delay-fault testing is becoming more important. The current delay-fault testing for FPGA is practiced by configuring the FPGA with different designs and running them at speed. It can't guarantee the performance of users' circuits since it is impossible to configure the FPGA with all possible designs.

Given the low overheads of implementing FPGA BIST and high cost of at-speed ATE, BIST for delay faults in FPGA is the preferred platform. In this thesis, we proposed a new BIST-based approach for FPGA interconnect delay faults. It can operate at rated clock speed and test most components on interconnects without being affected by clock skew. Thus, it has high delay fault detectability to test the faulty interconnects. Besides, it can be applied to FPGA manufacturing test because it can be independent of the end application. We will use Xilinx Spartan series FPGA to demonstrate the BIST structure, and evaluate our method by an efficient FPGA fault simulator. In our experiment, the fault coverage can be more than 98\% even under influence of
multiple delay defects. The total number of required test
configurations is 36 and independent of array size. Additionally, the overall test time is approximately 6.46
seconds.

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