卷積神經網路最近已在計算影像領域表現出突出的優勢。對於應用於動態影像超解析，它不但可以帶來更高的解析度還能有更好的視覺一致性，這對於下一代終端裝置像是電視來說會是不可或缺的。而動態影像超解析中最大的挑戰之一在於如何正確對齊相鄰幀。最近的研究，例如EDVR 和TDAN，應用可變形卷積來自適應地藉由偏移量去學習如何對齊並能在動態影像超解析中獲得更好的品質。可變形卷積使用與輸入相關的偏移量來獲得可遠離原規則地鄰近區域的新位置。然而，在終端裝置上實現可變形卷積時，仍有兩個主要挑戰需要解決。
首先，可變形卷積需要額外的晶片上儲存空間來解決由於位置不受約束而導致對輸入特徵圖的不規則提取的問題。然而，將整個輸入特徵圖存在晶片上儲存空間中對於終端裝置來說是無法負擔的。其次，在可變形卷積中獲取新位置時，使用到了雙線性插值法來處理落在非整數點上的位置。雙線性插值法的總計算量與偏移量的位寬和輸入特徵圖的大小成正比，這將在硬體實現上產生相當大的額外運算負擔。
因此，本文分別提出了兩種方法來解決上述對應問題。對於前者，我們提出了一個位置受限的可變形卷積，它將參考位置限制在絕對值範圍1 內以減少在獲得新參考位置時所需的晶片上儲存容量同時又維持在相似的影像品質。對於後者，我們進一步優化偏移量的位寬以減少雙線性插值法的運算負擔。此外，在台積電40 奈米製程技術下，我們以FHD 四倍動態影像超解析每秒30幀規格的eCNN 引擎作為基準，來驗證我們提出的方法。在峰值訊噪比僅下降0.01dB 的情況下，當應用我們提出的限制位置可變形卷積在範圍為1 時，我們可以將晶片上儲存空間大小從16.59MB 減少到0.07MB，這是原始可變形卷積0.4%。此外，可變形卷積中的雙線性插值法原需額外的718 萬個邏輯閘來支持8 位寬的偏移值。通過優化偏移值的位寬，在峰值訊噪比下降僅為0.07dB 的情況下，我們可以將偏移值的位寬降低到4 位，也就是降到380 萬個邏輯閘。總之，與作為基準的eCNN 引擎相比，我們的位置限制可變形卷積引擎在將偏移值從8 位元減少到4 位元時，可以將額外的面積負擔從39.9% 減少到23.7% 同時維持相似的影像品質。

Convolutional Neural Networks (CNNs) recently have shown prominent superiority in computational imaging. For application in video super-resolution (VSR), it can support higher resolution and bring better visual consistency, which may be indispensable to the next generation of edge devices such as TVs. One of the biggest challenges in VSR is to align neighboring frames properly. Recent studies, such as EDVR and TDAN, have applied the Deformable Convolution (DC) to learn the alignment by offsets adaptively and achieve better quality in VSR. DC uses the input-dependent offsets to obtain new locations away from its regular local neighborhood. However, when it comes to implementing DC on edge devices, there exist two main challenges to be solved.

To begin with, DC needs additional on-chip memory to solve the problem of irregular access on input feature maps caused by unconstrained locations. However, storing the whole input feature maps in on-chip memory is unaffordable for edge devices. Second, when obtaining a new location in DC, bilinear interpolation is used to process locations that fall on non-integer points. The total computation of bilinear interpolation is proportional to the bit width of offsets and size of input feature maps, which will incur a considerable computational overhead on hardware implementation.

Therefore, this thesis proposes two methods to deal with the above problems, respectively. For the former, we propose a location-confined DC (LCDC) that confines the reference locations to a constrained range 1 to reduce the on-chip storage required with similar quality when obtaining new reference locations. For the latter, we further optimize the bit width of offsets to reduce the computational overhead in bilinear interpolation. Furthermore, we take eCNN with the specification of VSRx4 FHD resolution 30fps under TSMC 40nm process technology as our baseline engine to verify our proposed methods. When applying LCDC engine, we can reduce the on-chip SRAM size from 16.59MB to 0.07MB which is 0.4% of the original DC with only 0.01dB PSNR drop. Moreover, the bilinear interpolation function in DC needs additional 7.18M gates to support the 8-bit offsets. By optimizing the bit width of offsets, we can reduce the bit width of offsets to 4-bit and cost 3.8M gates with only 0.07dB PSNR drop. In conclusion, the area overhead of our LCDC engine compared to the baseline eCNN engine can be reduced from 39.9% to 23.7% with similar quality when reducing offsets from 8-bit to 4-bit.

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