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研究生: 劉守恩
Shou-En Liu
論文名稱: 非對稱型雙閘極電晶體的臨界電壓模型
Threshold Voltage Model of Asymmetry Double Gate MOSFET
指導教授: 連振炘
Chen-Hsin Lien
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 61
中文關鍵詞: 非對稱型雙閘極電晶體臨界電壓量子侷限效應
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  • 由於非對稱型雙閘極電晶體的臨界電壓模型仍未完善,除了定義上有待修正以外,目前為止被提出的模型並未考慮到因維度縮小導致的量子效應問題。本論文中,將運用半導體物理之計算與MEDICI模擬軟體討論前非對稱型雙閘極臨界電壓模型的恰當性與量子效應造成的影響,將模型修正項以一半導體厚度與絕緣層厚度的參數表示,再輔以模擬軟體驗證之,以期能得到一易於使用的臨界電壓模型。與此則元件設計者將易於估算元件設計時所需要的元件參數。


    目錄 誌謝 摘要 目錄 圖表目錄 重要變數與其物理意義對照表 第一章 導論 .....................................1 1-1 研究動機 .......................................1 1-2 雙閘極電晶體的結構與特性 ........................4 1-3 非對稱型雙閘極電晶體的臨界電壓模型與問題 ........7 1-4 MEDICI 模擬環境介紹 .............................8 1-5 本論文目標架構 .................................10 第二章 雙閘極電晶體的臨界電壓模型 ...............11 2-1 對稱型雙閘極電晶體的臨界電壓模型 ...............11 2-2 非對稱型雙閘極電晶體的臨界電壓模型 .............18 2-3 不考慮量子效應時,非對稱型雙閘極電晶體的臨界電壓模型修正項 ..........................................22 2-3-1 模型的不恰當性與臨界電壓修正項 ...............22 2-3-2 模型與模擬比較 ...............................25 2-4 結論 .........................................28 第三章 考慮量子效應對臨界電壓的影響與修正 ......29 3-1 量子效應對雙閘極元件臨界電壓的影響...............29 3-2 量子效應對狀態上電子密度造成的影響及改變 ........32 3-3 考慮量子效應時,非對稱雙閘極電晶體的臨界電壓模型修正項 ..............................................38 3-3-1 考慮量子效應的臨界電壓修正項推導 ............38 3-3-2 模型與模擬比較 ..............................41 3-4 考慮高階能態占據電子對臨界電壓漂移的修正 ........42 3-4-1 較低能量能谷的第二能階 ......................45 3-4-2 較高能量能谷的最低能階 ......................45 3-4-3 考慮高階電子和模擬結果的比較 ................47 3-5 完整臨界電壓模型與討論 ..........................50 3-6 前後絕緣層厚度之不對稱效應 ......................54 3-7 結論 ............................................57 第四章 結論 ....................................58

    參考文獻
    References

    [1] S.H. Lo, D.A. Buchanan, Y. Taur, W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s”, IEEE Trans. on Electron Device Letters vol. 18, pp. 209-211, May 1997.

    [2] P. Wong, ”Beyond the Conventional Transistor”, IBM J. Res. & Dev., pp. 133-168, March/May 2002

    [3] ITRS, International Technology Roadmap for Semiconductors, 2003 edition.

    [4] K. Suzuki, T. Sugii, “Analytical Models for n+-p+ Double-Gate SOI MOSFET’s”, IEEE Trans. on Electron Devices, Vol. 42, pp.1940-1947, November 1995.

    [5] L. Chang, S. Tang, T.J. King, J. Bokor, C. Hu, “Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs”, IEDM, pp. 719-722, 2000.

    [6] M. Wong, X. Shi, “On the Threshold of symmetrical DG MOS Capacitor With Intrinsic Silicon Body”, IEEE Trans. on Electron Devices, Vol. 51, pp. 1600-1604, October 2004.

    [7] X. Shi, M. Wong, “Effects of Substrate Doping on the Linearly Extrapolated Threshold Voltage of Symmetrical”, IEEE Trans. on Electron Devices, Vol. 52, pp. 1616-1621, July 2005.

    [8] S.S. Chen, J.B. Kuo, “Deep Submicrometer Double-Gate Fully-Depleted SOI PMOS Devices: A Concise Short-Channel Effect Threshold Voltage Model Using a Quasi-2D Approach”, IEEE Trans. on Electron Devices, Vol. 43, pp. 1387-1393, September 1996.

    [9] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, T. Itoh, “Analytical surface potential expression for thin-film double-gate SOI MOSFET’s”, Solid-State Electron., vol.37, pp. 327-332, 1994.

    [10] Y. Taur, “An Analytical Solution to a Double-Gate MOSFET with Undoped Body”, IEEE Trans. on Electron Device Letters, Vol. 21, May 2000.

    [11] B. Majkusiak, T. Janik, J. Walczak, “Semiconductor Thickness effects in the Double-Gate SOI MOSFET”, IEEE Trans. on Electron Devices, Vol. 45, pp.1127-1134, May 1998.

    [12] M. J. Van Dort, P. H. Woerlee, A. J. Walker, “A Simple Model for Quantization Effects in Heavily-Doped Silicon MOSFETs at Inversion Condition”, Solid-State Electronics, Vol. 37. No. 3, pp.411-414, March 1994.

    [13] Y. Taur, “Analytic Solutions of Charge and Capacitance in Symmetric and Asymmetric Double-Gate MOSFETs”, IEEE Trans. on Electron Devices, Vol. 48, pp.2861-2869, December 2001.

    [14] Q. Chen, Evans M. Harrell, James D. Meindl, “A Physical Short-Channel Threshold Voltage Model for Undoped Symmetric Double-Gate MOSFET”, IEEE Trans. on Electron Devices, Vol. 50, pp.1631-1636, July 2003.

    [15] Y. Ma, Z. Li, L. Liu, L. Tian, Z. Yu, “Effective density-of-states approach to QM correction in MOS structures”, Solid-State Electron. Vol. 44, pp.401-407, 2000.

    [16] X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.K. Choi, K. Asano, V. Subramanian, T.J. King, J. Bokor, C. Hu, “Sub 50-nm FinFET: PMOS”, IEDM, pp.67-70, 1999.

    [17] Q. Chen, L. Wang, James D. Meindl, “Quantum Mechanical Effects on Double-Gate MOSFET Scaling”, IEEE SOI Conference, pp.213-214, October 2002.

    [18] L. Ge, Jerry G. Fossum, “Analytical Modeling of Quantization and Volume Inversion in Thin Si-Film DG MOSFETs”, IEEE Trans on Electron Devices, Vol. 49, pp.287-294, February 2002.

    [19] Vishal P. Trivedi, Jerry G. Fossum, “Quantum-Mechanical Effects on the Threshold Voltage of Undoped Double-Gate MOSFETs”, IEEE Trans on Electron Device Letters, Vol. 26, pp.579-582, August 2005.

    [20] G. Baccarani, S. Reggiani, “A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects”, IEEE Trans. Electron Devices, Vol. 46, pp.1656-1666, August 1999.

    [21] F. Stern and W. E. Howard, “Properties of semiconductor surface inversion layers in the electric quantum limit”, Phys. Rev. 163, p.816, 1967.

    [22] Y. Taur and Tak H. Ning, “Fundamentals of Modern VLSI Devices”, 1998.

    [23] F. Stern, ”Self-consistent results for n-type Si inversion layers”, Phys. Rev. B 5, p.4891, 1972.

    [24] K. Kim, Jerry G. Fossum, “Double-Gate CMOS: Symmetrical- Versus Asymmetrical- Gate Devices”, IEEE Trans. on Electron Devices, Vol.48, pp. 294-299, February 2001.

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