隨著科技快速的發展，通訊系統對於資料傳輸的速度及精確度的規格需求更加苛刻，使得設計更快速的高速電路架構成為當代工程師的目標，5G通訊技術提供極高的傳輸速度，使人類在進行通話時有更好的品質，以及透過視訊來面對面交談，而在這些通訊技術的應用背後，類比數位轉換器是系統中不可或缺的電路，是唯一可以將生活中的類比訊號轉換成數位訊號的電路，針對不同應用，衍生出許多不同類型的類比數位轉換器，而隨著半導體製程的演進，連續漸進式類比數位轉換器成為近年來熱門的選擇。
本論文實現了一個高速帶冗餘位連續漸進式類比數位轉換器，在每秒八千萬次取樣的速度下，使用了帶冗餘位演算法的概念達到速度上的提升，並且提出一個新穎的數位邏輯控制電路來更進一步減少轉換過程的延遲。此類比數位轉換器具有高速的特性，可以用於時序交錯式的類比數位轉換器，透過通道並聯的特性，達到速度上的提升。
本論文之十二位元連續漸進式類比數位轉換器利用台積電六五奈米的CMOS製程來設計，最高取樣頻率為每秒八千萬取樣點，操作電壓為1.2V，軌對軌輸入訊號的振幅為1.8V，模擬結果中訊號與雜訊諧波比可達到70.48dB，相當於有效位元為11.4，DNL為+0.03/-0.03LSB，INL為+0.04/-0.05 LSB，平均消耗功率為3.554mW。

The lives of humans have undergone significant changes due to the evolution of wireless
communication technology. 5th generation wireless system provides extremely high data transmission
speeds. Enabling humans to have a better quality when conducting calls, and face-to-face
conversations through video. Behind these applications, the analog-to-digital converter is an
indispensable circuit in the system. It is the only circuit that can convert the analog signal in life into
a digital signal. For different applications, many different types of analog-to-digital converters are
derived. With the scaling of semiconductor manufacturing processes, the Successive Approximation
Register Analog-to-Digital Converters have become a popular choice in recent years.
In the thesis, we have proposed a high-speed SAR ADC. It combines the redundancy algorithm
to speed up the conversion rate and does not increase the capacitance of sampling capacitor .A novel
digital logic control circuit is proposed to further decrease the delay of conversion.
The 12 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1.2V supply
voltage. The full rail-to-rail input swing is 1.8V peak to peak. This design achieve signal to noise and
distortion ratio of 70.48dB, equivalent to the effective number of bits 11.4. The peak DNL values are
-0.03 to +0.03 LSB and the peak INL values are -0.05 to +0.04 LSB. The average power consumption
is 3.554mW.

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